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Eda Tuncel

from Menlo Park, CA
Age ~65
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Also known as:
Eda Miles, Edna Tuncel, Eda Tunce, Eda O
Phone and address:
949 Fremont St, Menlo Park, CA 94025
(650) 329-1464
Related to:
Ronald Miles, 84
Connected to:
Ece Tuncel, 48Umur Tuncer, 45Nukte Tuncok, 43Matthew O Tunde, 46Nicole R Tunder, 43Lena Tundis, 63Douglas A Tundo, 68Alan M Tune, 46Ann R Tune, 68Darren R Tune, 51

Eda Tuncel Phones & Addresses

  • 949 Fremont St, Menlo Park, CA 94025 (650) 329-1464 (650) 704-1674
  • Napa, CA
  • Felton, CA
  • 949 Fremont St, Menlo Park, CA 94025 (650) 329-1464

Resumes

Resumes

Eda Tuncel Photo 1

Senior Application Engineer

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Location:
Palo Alto, CA
Industry:
Semiconductors
Work:
Agilone Nov 2012 - Sep 2014
Db Analyst
Mosel Vitelic Corporation Mar 2004 - Apr 2006
Staff Process Engineer
Stanford University Jan 1995 - Jan 1998
Visiting Scholar
Applied Materials Jan 1995 - Jan 1998
Senior Application Engineer
Education:
Catholic University of America
Master of Science, Masters Epfl (École Polytechnique Fédérale De Lausanne)
Bachelors, Bachelor of Science, Physics The Catholic University of America
Master of Science, Masters, Physics Epfl (École Polytechnique Fédérale De Lausanne)
Doctorates, Doctor of Philosophy, Physics, Philosophy
Skills:
Semiconductors
Thin Films
Spc
Metrology
Design of Experiments
Analytics
Plasma Etch
Epitaxy
Inline Cd Sem
Languages:
French
Turkish
Eda Tuncel Photo 2

Semiconductors Professional

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Location:
San Francisco Bay Area
Industry:
Semiconductors
Eda Tuncel Photo 3

Sr. Process Eng. At Applied Materials

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Position:
Sr. Process Eng. at Applied Materials
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Applied Materials
Sr. Process Eng.

Publications

Us Patents

Selective Self-Aligned Double Patterning Of Regions In An Integrated Circuit Device

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US Patent:
8293656, Oct 23, 2012
Filed:
Jul 17, 2009
Appl. No.:
12/505404
Inventors:
Hun Sang Kim - San Ramon CA, US
Hyungje Woo - Cupertino CA, US
Shinichi Koseki - Palo Alto CA, US
Eda Tuncel - Menlo Park CA, US
Chung Liu - San Jose CA, US
Assignee:
Applied Materials, Inc. - Santa Clara CA
International Classification:
H01L 21/302
US Classification:
438736, 438714, 438725, 438735
Abstract:
A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask.

Ashable Layers For Reducing Critical Dimensions Of Integrated Circuit Features

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US Patent:
20030219988, Nov 27, 2003
Filed:
May 22, 2002
Appl. No.:
10/154532
Inventors:
Hongqing Shan - Cupertino CA, US
Kenny Doan - San Jose CA, US
Jingbao Liu - Sunnyvale CA, US
Michael Barnes - San Ramon CA, US
Huong Nguyen - San Ramon CA, US
Christopher Bencher - San Jose CA, US
Christopher Ngai - Burlingame CA, US
Wendy Yeh - Mountain View CA, US
Eda Tuncel - Menlo Park CA, US
Claes Bjorkman - Mountain View CA, US
Assignee:
Applied Materials, Inc.
International Classification:
H01L021/302
H01L021/461
US Classification:
438/725000, 438/947000, 438/950000
Abstract:
A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer () is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer () is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer () underlying the topmost masking layer () from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer. Substructures formed in the fabrication process are also described. Spacers are also shown to be favorably employed in making feature-in-feature structures.

Line Edge Roughness Control

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US Patent:
20090057266, Mar 5, 2009
Filed:
Aug 27, 2007
Appl. No.:
11/845613
Inventors:
Eda Tuncel - Menlo Park CA, US
George Kovall - Campbell CA, US
International Classification:
H01L 21/302
US Classification:
216 41
Abstract:
In one embodiment, a method includes providing a plasma etch reactor including a vacuum chamber and an electrode disposed inside of the chamber, and providing a stack to be etched over the electrode, the stack including a patterned photoresist over a dielectric layer. The method further includes providing a chamber pressure between about 75 mT and about 150 mT, flowing gases including CFand CHFat a ratio between about 2.5:1 and about 5.0:1 into the chamber, applying RF power to the electrode between about 300 W and about 500 W to form a plasma from the gases, and etching the dielectric layer with the plasma through the patterned photoresist.

Multiple Complementary Gas Distribution Assemblies

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US Patent:
20130098455, Apr 25, 2013
Filed:
Oct 11, 2012
Appl. No.:
13/649488
Inventors:
Yuriy Melnik - San Jose CA, US
Lily L. Pang - Fremont CA, US
Eda Tuncel - Menlo Park CA, US
Lu Chen - Cupertino CA, US
Son T. Nguyen - San Jose CA, US
International Classification:
C23C 16/455
US Classification:
137 1, 137561 R
Abstract:
Described herein are exemplary apparatuses having multiple gas distribution assemblies in accordance with one embodiment. In one embodiment, the apparatus includes two or more gas distribution assemblies. Each gas distribution assembly has orifices through which at least one process gas is introduced into a processing chamber. The two or more gas distribution assemblies may be designed to have complementary characteristic radial film growth rate profiles.

Methods And Apparatus For Detecting An Endpoint Of A Seasoning Process

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US Patent:
20190348312, Nov 14, 2019
Filed:
May 3, 2019
Appl. No.:
16/403104
Inventors:
- Santa Clara CA, US
Eda TUNCEL - Menlo Park CA, US
Shayne SMITH - Pflugerville TX, US
Liming ZHANG - San Jose CA, US
Sathyendra GHANTASALA - Fremont CA, US
Ryan PATZ - Swampcott MA, US
International Classification:
H01L 21/67
G05B 13/02
G05B 19/418
Abstract:
A method for detecting an endpoint of a seasoning process in a process chamber includes obtaining seasoning progress data indicating a progress of the seasoning process for each substrate of a first plurality of substrates, and collecting historical parameter values from a plurality of sensors disposed in the process chamber. The historical parameter values for each substrate of the first plurality of substrates are normalized with respect to a plurality of parameter values for a particular substrate in the first plurality of substrates. An MVA model is generated by applying a set of coefficients to the normalized parameter values for each substrate of the first plurality of substrates, and the set of coefficients are regressed based on the seasoning progress data. An end point of the seasoning process is determined using the MVA model with a plurality of substantially real-time parameter values measured when performing a seasoning process over each substrate of a second plurality of substrates.
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Eda Tuncel from Menlo Park, CA, age ~65 Get Report