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Dustin E Flay

from Phoenixville, PA
Age ~62
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Also known as:
Dustin E Slay, Flay Flay, Flay Dustin
Related to:
Jared P Flay, 45William H Trexler, 60Lisa Argento FlayJoseph P ArgentoHendrika C Trexler, 60Lisa A Flay, 61Jennie H Flay, 93Rosemari F Argento, 89Katalina RodriguezDawn W Trexler, 63Thomas H Martell, 77Dean H Flay
Connected to:
Paula M Flay, 76Timothy P Flay, 55Judy R Flayderman, 65Paul W Flayler, 74Gordon P Flayter, 77Nathalie Flaz, 38Kieara L Fleagle, 33Megan E Fleagle, 35Morgan L Fleagle, 33Gary Fleahman, 71

Dustin Flay Phones & Addresses

  • Phoenixville, PA
  • 77 Bethel Church Rd, Spring City, PA 19475 (484) 938-7817
  • Parker Ford, PA
  • Chester, PA
  • 66 Jennifer Dr, Chester Sprgs, PA 19425 (610) 594-2583
  • Chester Springs, PA
  • Glenmoore, PA
  • Downingtown, PA
  • York, PA

Work

Company: Honeywell Jul 2017 Position: Senior principal hw engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Lehigh University 1981 to 1985 Specialities: Electrical Engineering

Skills

Hardware Architecture • Electronics • Engineering • Electrical Engineering • Fpga • Automation • Embedded Systems • Debugging • Testing • Firmware • Product Development • Process Control • Pcb Design • Microcontrollers • C • Engineering Management • Embedded Software • Cpld • Telecommunications • Process Automation • Ethernet

Ranks

Certificate: Design For Six Sigma Greenbelt

Industries

Industrial Automation

Resumes

Resumes

Dustin Flay Photo 1

Senior Principal Hw Engineer

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Location:
4600 Business Park Blvd, Anchorage, AK 99503
Industry:
Industrial Automation
Work:
Honeywell
Senior Principal Hw Engineer
Honeywell
Team Lead and Principal Hw Engineer
Ctdi Dec 2009 - Dec 2010
Principal Engineer
Apex Systems Sep 2009 - Dec 2009
Electrical Engineering Consultant
Motorola Jun 2000 - Sep 2003
Principal Staff Engineer
Education:
Lehigh University 1981 - 1985
Bachelors, Bachelor of Science, Electrical Engineering Central York Senior Hs 1977 - 1981
Central Hs 1977 - 1981
Skills:
Hardware Architecture
Electronics
Engineering
Electrical Engineering
Fpga
Automation
Embedded Systems
Debugging
Testing
Firmware
Product Development
Process Control
Pcb Design
Microcontrollers
C
Engineering Management
Embedded Software
Cpld
Telecommunications
Process Automation
Ethernet
Certifications:
Design For Six Sigma Greenbelt

Publications

Us Patents

Multi-Level Electronic Protection System Providing Safe Fault Recovery For Multiple Digital Control Outputs

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US Patent:
20090021880, Jan 22, 2009
Filed:
Jul 16, 2007
Appl. No.:
11/778296
Inventors:
Dustin Flay - Chester Springs PA, US
Charles L. Martin - Blue Bell PA, US
Sunil M. Ingawale - Bangalore, IN
Assignee:
Honeywell International Inc. - Morristown NJ
International Classification:
H02H 3/00
US Classification:
361101
Abstract:
A multi-level over-current electronic protection system for protecting a plurality of outputs includes a first solid state reversibly interruptible electronic switch including first output control logic and a plurality of first controlled output channels controlled by the first control logic. The first switching device is coupled to receive power from at least one power supply selected to power a plurality of loads. The first switching device provides power at its plurality of first output channels under normal operating conditions, wherein the first output control logic is operable for reversibly interrupting power at any of the first output channels when current in any of the first output channels exceed limits for the first output channels. At least one second solid state reversibly interruptible electronic switch including second control logic and a plurality of second controlled outputs control by the second control logic is also provided. A power supply input of the second switch is coupled to one of the plurality of first controlled output channels to receive the power, wherein the second controlled outputs are coupled to provide the power to the plurality of loads under normal operating conditions and reversibly interrupting the power for any of the second output channels when current in any of said second output channels exceeds limits for the second output channels. A CPU having associated firmware can be coupled to the second output channels and external inputs of the second switches via an isolation device to provide a supervisory and monitoring function.

Method And Apparatus For Providing Early Warning Of Extraction Of Module Under Power

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US Patent:
20160116521, Apr 28, 2016
Filed:
Dec 19, 2014
Appl. No.:
14/577521
Inventors:
- Morristown NJ, US
Dustin Flay - Spring City PA, US
International Classification:
G01R 31/04
Abstract:
An apparatus includes a connector configured to be electrically coupled to electrical circuitry. The connector has multiple pins, including one or more first pins and one or more second pins. The one or more second pins longer than the one or more first pins. The apparatus also includes a signal generator configured to detect disconnection of the one or more first pins prior to disconnection of the one or more second pins and generate a signal in response to detecting the disconnection of the one or more first pins. The connector could also include one or more third pins longer than the one or more second pins. The first pin(s) can create an electrical path from the signal generator to ground, the second pin(s) can provide a supply voltage to the electrical circuitry, and the third pin(s) can electrically couple the electrical circuitry to ground.
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Dustin E Flay from Phoenixville, PA, age ~62 Get Report