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Duane G Quiet

from Hillsboro, OR
Age ~58
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Also known as:
Duane Gregory Quiet, Duane G Quite
Phone and address:
3563 Pine St, Beaverton, OR 97123
(503) 844-9074
Connected to:
Brandy N Quiet, 38Coral A Quiet, 120Stephan L Quiet, 43Tawnya Quiet, 60Taylor J Quiet, 32Marvin Quieta, 35Amanda D Quiett, 49Joe A Quiett, 58Abbas N Quigee, 36Brandi Quigg, 43

Duane Quiet Phones & Addresses

  • 3563 Pine St, Hillsboro, OR 97123 (503) 844-9074
  • Gorham, ME
  • 723 Riverside St, Portland, ME 04103
  • 3563 SE Pine St, Hillsboro, OR 97123 (541) 513-6351

Work

Company: Intel corporation 1995 Position: Principal engineer at intel corporation

Education

Degree: Associate degree or higher

Skills

High Speed I/O • Imaging • Platform Timing • Semiconductors • Mixed Signal Ic Design

Emails

d***[email protected]

Industries

Semiconductors

Resumes

Resumes

Duane Quiet Photo 1

Principal Engineer At Intel Corporation

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation
Principal Engineer at Intel Corporation
Skills:
High Speed I/O
Imaging
Platform Timing
Semiconductors
Mixed Signal Ic Design

Publications

Us Patents

Modifying Acoustic Emissions Of Fans

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US Patent:
6720756, Apr 13, 2004
Filed:
Nov 5, 2001
Appl. No.:
09/991619
Inventors:
Harry G. Skinner - Beaverton OR
Duane G. Quiet - Hillsboro OR
Willem M. Beltman - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01N 2700
US Classification:
324 711
Abstract:
In one embodiment to reduce unwanted acoustic fan noise, the control signal for a computer system cooling fan is modulated so that the acoustic noise power spectral density of the fan has a bandwidth greater than when the control signal is constant.

Noise Injection Method To Characterize Common-Clock Timing Margins

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US Patent:
6826495, Nov 30, 2004
Filed:
Sep 28, 2001
Appl. No.:
09/968462
Inventors:
Duane Quiet - Hillsboro OR
Garrett Hall - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 2300
US Classification:
702 75, 702 69, 324 7619, 327 21, 327144
Abstract:
A noise injection method for characterizing common clock timing margin (jitter) includes injecting a single tone frequency, varying the amplitude of the injected frequency; measuring the signal produced at various signal amplitudes and analyzing the data obtained from measuring the signal. The obtained measurements may be analyzed using various characterizations such as measured jitter on input, measured jitter transfer, measured jitter tolerance, etc.

Scalable Method And Apparatus For Link With Reconfigurable Ports

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US Patent:
8296469, Oct 23, 2012
Filed:
May 13, 2009
Appl. No.:
12/454155
Inventors:
Robert Dunstan - Forest Grove OR, US
Ajay Bhatt - Portland OR, US
Duane Quiet - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 3/00
US Classification:
710 8, 710105, 710106
Abstract:
Disclosed herein are reconfigurable ports and methods for doing the same.

Spread Spectrum Clock Generator

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US Patent:
8045666, Oct 25, 2011
Filed:
Mar 22, 2007
Appl. No.:
11/726911
Inventors:
Vishnu Balraj - Folsom CA, US
Terry Baucom - El Dorado Hills CA, US
Amir Bashir - El Dorado Hills CA, US
Huimin Chen - Portland OR, US
Ken Drottar - Portland OR, US
Naveed Khan - Folsom CA, US
Duane Quiet - Hillsboro OR, US
Andrew M. Volk - Granite Bay CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 7/00
US Classification:
375371
Abstract:
Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Asymmetric Link For Streaming Applications

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US Patent:
20120300085, Nov 29, 2012
Filed:
May 23, 2011
Appl. No.:
13/113821
Inventors:
Huimin Chen - Portland OR, US
Duane G. Quiet - Hillsboro OR, US
David J. Harriman - Portland OR, US
International Classification:
H04N 7/173
H04N 5/225
US Classification:
3482071, 725127, 348E05024
Abstract:
Systems and methods of supporting video streaming operations may involve transmitting a pulse width modulated (PWM) control signal to an imaging device, wherein the imaging devices identifies control data based on a duty cycle of the control signal. The imaging device can configure a video stream based on the control data and synchronize transmission of the video stream based on a frequency of the control signal.

Scalable Method And Apparatus To Configure A Link

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US Patent:
20130046908, Feb 21, 2013
Filed:
Oct 19, 2012
Appl. No.:
13/655916
Inventors:
Robert Dunstan - Forest Grove OR, US
Ajay Bhatt - Portland OR, US
Duane Quiet - Hillsboro OR, US
International Classification:
G06F 13/00
US Classification:
710104
Abstract:
Disclosed herein axe reconfigurable ports and methods for doing the same.

Gradual Frequency Changing Circuit

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US Patent:
55921132, Jan 7, 1997
Filed:
Mar 28, 1995
Appl. No.:
8/412270
Inventors:
Duane G. Quiet - Portland ME
E. Wayne Porter - Portland ME
Assignee:
National Semiconductor Corp. - Santa Clara CA
International Classification:
H03L 706
US Classification:
327158
Abstract:
An error-limiting circuit for regulating the time required to bring the output signal of a control system such as a phase-locked loop device into conformance with a reference input signal. For a phase-locked loop system the error-limiting circuit is a phase-error-limiting circuit that provides for a gradual changing of the signal frequency of a voltage-controlled oscillator of the phase-locked loop device so that frequency synchronization of subsequent devices coupled to the phase-locked loop with the reference signal is ensured. The phase-error-limiting circuit forms part of the phase-frequency detector that is coupled to a charge pump that outputs current to a loop filter that in turn effectively controls the voltage-controlled oscillator. The phase-error-limiting circuit acts to assert or de-assert as required an error-correcting UP or DOWN signal to the charge pump. While the charge supplied by the charge pump is normally dependent only on the phase difference between the reference signal and the VCO signal, the phase-error-limiting circuit cuts in to control the UP or DOWN signal duration when the phase difference exceeds some pre-selected value.

Lock Sensor Circuit And Method For Phase Lock Loop Circuits

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US Patent:
53049527, Apr 19, 1994
Filed:
May 10, 1993
Appl. No.:
8/060100
Inventors:
Duane G. Quiet - Gorham ME
Ray A. Mentzer - Portland ME
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03L 7089
H03L 7095
US Classification:
331 1A
Abstract:
A lock sensor circuit detects and indicates occurrence of a phase lock condition of an output signal of a phase lock loop (PLL) circuit when the PLL output signal is phase locked to a reference signal. A phase and frequency detector (PFD) has a reference signal input (REF IN) and a feedback signal input (VCO FBK IN) coupled to the output of the PLL circuit. The PFD delivers output UP and DOWN signals according to whether the reference signal leads or lags the feedback signal. A multi-bit up/down counter (FIG. 2 ) has UP and DOWN inputs coupled to the respective UP and DOWN outputs of the PFD and an m bit output (Q0, Q1,. . . Q10). A lock sensor circuit (50) coupled to the m bit up/down counter monitors the nth bit output (QN) of the up/down counter where n
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Duane G Quiet from Hillsboro, OR, age ~58 Get Report