Search

Dominic Setiadi Suryabudi

from Irvine, CA
Age ~48
Get Report
Also known as:
Dominic S Suryabudi
Phone and address:
32 Sweet Shade, Irvine, CA 92606
Related to:
Erik E Johnson, 54Jean T Johnston, 66Caroline SuryabudiCaroline Suryabudi, 45Van P Johnston, 56Caroline Suryabudi, 40William S Suryabudi, 51
Connected to:
Gopinath Suryadevara, 40Vikranthi Suryadevara, 50Dicky Suryadi, 51Iwan Suryadi, 52Roy Suryadipta, 54William H Suryajaya, 42Roopa Suryanarayana, 45Savithri Suryanarayanan, 69Sharath Suryanarayan, 47Sridhara B Suryanarayana, 60

Dominic Suryabudi Phones & Addresses

  • 32 Sweet Shade, Irvine, CA 92606
  • 131 Santa Barbara, Irvine, CA 92606
  • 2760 Kelvin Ave #3213, Irvine, CA 92614 (765) 495-2855
  • 1301 Richmond Ave, Houston, TX 77006 (713) 523-8483
  • 1301 Richmond Ave #E E 2, Houston, TX 77006 (713) 523-8483
  • 1301 Richmond Ave #E2, Houston, TX 77006 (713) 523-8483
  • 340 Lawn Ave, West Lafayette, IN 47906
  • 929 Cary Quad #233, West Lafayette, IN 47906 (765) 495-2855
  • 946 Cary Quad #SE362, West Lafayette, IN 47906 (765) 495-2855
  • Orange, CA
  • W Lafayette, IN

Work

Company: Masimo Mar 2019 Position: Embedded software manager

Education

Degree: Master of Science, Masters School / High School: Purdue University Specialities: Computer Engineering

Skills

Firmware • Sata • Ssd • C • Arm • Digital Signal Processors • Rtos • Nand Flash • Embedded Systems • Testing • C++ • Debugging • Embedded Software • Jtag • Emmc • Scsi • Usb • Logic Analyzer • Emulator • Badminton • Svn • Processors • Software Design • Assembly Language • 8051 Microcontroller • Atmel Avr • Microcontrollers • Device Drivers • Software Engineering • Solid State Hybrid Drive • Software Architectural Design • I2C • Spi • Sas • Uart • Rs232 • Msp430 • Embedded Linux • Storage • Linux • Soc

Industries

Medical Devices

Resumes

Resumes

Dominic Suryabudi Photo 1

Embedded Software Manager

View page
Location:
Irvine, CA
Industry:
Medical Devices
Work:
Masimo
Embedded Software Manager
Masimo
Senior Software Engineer
Western Digital Mar 2009 - May 2013
Senior Principal Firmware Engineer, Ssd and Sshd Hybrid Storage
Silicon Systems Oct 2008 - Mar 2009
Senior Firmware Engineer
Owlink Technologies, Inc Jul 2006 - Sep 2008
Senior Firmware Engineer
Education:
Purdue University
Master of Science, Masters, Computer Engineering Purdue University
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Firmware
Sata
Ssd
C
Arm
Digital Signal Processors
Rtos
Nand Flash
Embedded Systems
Testing
C++
Debugging
Embedded Software
Jtag
Emmc
Scsi
Usb
Logic Analyzer
Emulator
Badminton
Svn
Processors
Software Design
Assembly Language
8051 Microcontroller
Atmel Avr
Microcontrollers
Device Drivers
Software Engineering
Solid State Hybrid Drive
Software Architectural Design
I2C
Spi
Sas
Uart
Rs232
Msp430
Embedded Linux
Storage
Linux
Soc

Publications

Us Patents

Non-Volatile Semiconductor Memory Segregating Sequential Data During Garbage Collection To Reduce Write Amplification

View page
US Patent:
8316176, Nov 20, 2012
Filed:
Feb 17, 2010
Appl. No.:
12/707552
Inventors:
Lan D. Phan - Laguna Hills CA, US
Dominic S. Suryabudi - Irvine CA, US
Assignee:
Western Digital Technologies, Inc. - Irvine CA
International Classification:
G06F 12/00
US Classification:
711103, 36518533
Abstract:
A non-volatile semiconductor memory is disclosed comprising a memory device including a memory array having a plurality of blocks, each block comprising a plurality of memory segments. A plurality of logical block address (LBA) ranges are defined each identifying a plurality of LBA addresses, wherein at least one block is assigned to each LBA range. A plurality of write commands are received from a host, wherein each write command identifies at least one LBA. Data is written for each write command to the memory device. During a garbage collection operation, a memory segment storing valid write data is identified to be relocated, and the valid write data is relocated to a memory segment in a block of the corresponding LBA range.

Sequential Write Thread Detection

View page
US Patent:
8458435, Jun 4, 2013
Filed:
Dec 20, 2010
Appl. No.:
12/973085
Inventors:
Dominic S. Suryabudi - Irvine CA, US
Assignee:
Western Digital Technologies, Inc. - Irvine CA
International Classification:
G06F 12/00
US Classification:
711203, 711103, 711114, 711202
Abstract:
Embodiments of the invention are directed to systems and methods for detecting sequential write threads in non-volatile storage media. The embodiments described herein detect write commands directed to a range of logical addresses corresponding to a write thread. Upon detection of a write command directed to a write thread, the write command is assigned a physical write address associated with the write thread. Identification of write threads can be implemented with a hardware component which performs comparison operations between the write command address range and the write thread address range.

Flash Memory Device Comprising Host Interface For Processing A Multi-Command Descriptor Block In Order To Exploit Concurrency

View page
US Patent:
20120254504, Oct 4, 2012
Filed:
Mar 28, 2011
Appl. No.:
13/073638
Inventors:
Robert L. Horn - Yorba Linda CA, US
Virgil V. Wilkins - Perris CA, US
Dominic S. Suryabudi - Irvine CA, US
Assignee:
WESTERN DIGITAL TECHNOLOGIES, INC. - Irvine CA
International Classification:
G06F 12/00
US Classification:
711103, 711E12008
Abstract:
A flash memory device is disclosed comprising a flash controller for accessing a first flash memory over a first channel and a second flash memory over a second channel. A multi-command descriptor block is received from a host, wherein the multi-command descriptor block comprises identifiers for identifying a plurality of access commands that the host is preparing to request. A first group of the access commands are selected to execute concurrently and a second group of the access commands are selected to execute concurrently. The first group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently. The second group of access commands are received from the host and executed concurrently by accessing at least the first and second flash memories concurrently.

Non-Volatile Semiconductor Memory Module Enabling Out Of Order Host Command Chunk Media Access

View page
US Patent:
20120260020, Oct 11, 2012
Filed:
Apr 6, 2011
Appl. No.:
13/080800
Inventors:
DOMINIC S. SURYABUDI - IRVINE CA, US
Assignee:
WESTERN DIGITAL TECHNOLOGIES, INC. - Irvine CA
International Classification:
G06F 12/00
US Classification:
711103, 711E12008
Abstract:
A non-volatile semiconductor memory module is disclosed comprising a memory device and memory controller operably coupled to the memory device, wherein the memory controller is operable to receive a host command, split the host command into one or more chunks comprising a first chunk comprising at least one logical block address (LBA), and check the first chunk against an active chunk coherency list comprising one or more active chunks to determine whether the first chunk is an independent chunk, and ready to be submitted for access to the memory device, or a dependent chunk, and deferred access to the memory device until an associated dependency is cleared.

System Data Storage Mechanism Providing Coherency And Segmented Data Loading

View page
US Patent:
20210141543, May 13, 2021
Filed:
Jan 20, 2021
Appl. No.:
17/153719
Inventors:
- San Jose CA, US
Dominic S. SURYABUDI - Irvine CA, US
Lan D. PHAN - Laguna Hills CA, US
International Classification:
G06F 3/06
G06F 12/02
G06F 11/14
Abstract:
A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.

System Data Storage Mechanism Providing Coherency And Segmented Data Loading

View page
US Patent:
20190347017, Nov 14, 2019
Filed:
Jul 26, 2019
Appl. No.:
16/523951
Inventors:
- San Jose CA, US
Dominic S. SURYABUDI - Irvine CA, US
Lan D. PHAN - Laguna Hills CA, US
International Classification:
G06F 3/06
G06F 11/14
G06F 12/02
Abstract:
A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.

System Data Storage Mechansim Providing Coherency And Segmented Data Loading

View page
US Patent:
20160048352, Feb 18, 2016
Filed:
Oct 26, 2015
Appl. No.:
14/923000
Inventors:
- Irvine CA, US
Dominic S. SURYABUDI - IRVINE CA, US
Lan D. PHAN - Laguna Hills CA, US
International Classification:
G06F 3/06
Abstract:
A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.
Control profile
Dominic Setiadi Suryabudi from Irvine, CA, age ~48 Get Report