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Dieter D Dornisch

from Carlsbad, CA
Age ~64
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Also known as:
Dieter Dorisch, Dieter H
Phone and address:
2732 York Rd, Carlsbad, CA 92008
(760) 434-5248
Related to:
Deborah A Vanwieringen, 69Rebecca A Vanwieringen, 38Elisabeth Dornisch, 29Margit Dornisch, 63Anna Dornisch
Connected to:
Bradley S Dornish, 62Thomas Dornita, 87Westley E Dornseif, 82Danielle N Dornsife, 52Courtney W Dornstein, 43Jesse Dornstreich, 43Claudia R Doro, 52Deborah C Doro, 65Loni Doro, 35Christopher J Doroba, 33

Dieter Dornisch Phones & Addresses

  • 2732 York Rd, Carlsbad, CA 92008 (760) 434-5248 (760) 846-1020
  • Oceanside, CA
  • San Diego, CA
  • 2732 York Rd, Carlsbad, CA 92010

Work

Company: Jazz semiconductor Oct 2004 Position: Process engineering manager for diffusion, thin film, cmp

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Ludwig - Maximilians Universität München 1986 to 1991

Skills

Semiconductors • Thin Films • Spc • Characterization • Semiconductor Industry • Process Integration • R&D • Manufacturing • Process Engineering • Design of Experiments • Jmp • Electroplating • Materials Science • Metrology • Physics • Engineering Management • Process Simulation • Cmp • Ic • Silicon • Engineering • Materials • Failure Analysis • Nanotechnology • Electronics • Cvd • Afm • Statistical Process Control

Languages

English • German

Industries

Semiconductors

Resumes

Resumes

Dieter Dornisch Photo 1

Process Engineering Manager For Diffusion, Thin Film, Cmp

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Location:
Carlsbad, CA
Industry:
Semiconductors
Work:
Jazz Semiconductor
Process Engineering Manager For Diffusion, Thin Film, Cmp
Jazz Semiconductor Oct 1996 - Sep 2004
Principal Engineer R and D
Ipec/Athens Oceanside Ca Apr 1994 - Oct 1996
Senior Scientist
Metron Semiconductor Deutschland Germany Jul 1992 - Mar 1994
Sales Engineer
Education:
Ludwig - Maximilians Universität München 1986 - 1991
Doctorates, Doctor of Philosophy Ludwig - Maximilians Universität München 1979 - 1985
Skills:
Semiconductors
Thin Films
Spc
Characterization
Semiconductor Industry
Process Integration
R&D
Manufacturing
Process Engineering
Design of Experiments
Jmp
Electroplating
Materials Science
Metrology
Physics
Engineering Management
Process Simulation
Cmp
Ic
Silicon
Engineering
Materials
Failure Analysis
Nanotechnology
Electronics
Cvd
Afm
Statistical Process Control
Languages:
English
German

Publications

Us Patents

Integrated Circuit Plating Using Highly-Complexed Copper Plating Baths

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US Patent:
6709564, Mar 23, 2004
Filed:
Sep 30, 1999
Appl. No.:
09/410250
Inventors:
D. Morgan Tench - Camarillo CA
John T. White - Lancaster CA
Dieter Dornisch - Carlsbad CA
Maureen Brongo - Laguna Hills CA
Assignee:
Rockwell Scientific Licensing, LLC - Thousand Oaks CA
International Classification:
C25D 338
US Classification:
205291, 205293, 205296, 205298
Abstract:
The acid copper sulfate solutions used for electroplating copper circuitry in trenches and vias in IC dielectric material in the Damascene process are replaced with a type of plating system based on the use of highly complexing anions (e. g. , pyrophosphate, cyanide, sulfamate, etc. ) to provide an inherently high overvoltage that effectively suppresses runaway copper deposition. Such systems, requiring only one easily-controlled organic additive species to provide outstanding leveling, are more efficacous for bottom-up filling of Damascene trenches and vias than acid copper sulfate baths, which require a minimum of two organic additive species. The highly complexed baths produce fine-grained copper deposits that are typically much harder than large-grained acid sulfate copper deposits, and which exhibit stable mechanical properties that do not change with time, thereby minimizing âdishingâ and giving more consistent CMP results. The mechanical properties and texture of the fine-grained deposits are also much less substrate dependent, which minimizes the effects of variations and flaws in the barrier and seed layers. The resistivity of pyrophosphate and annealed acid sulfate copper deposits are approximately equivalent.

High-K Dielectric Stack In A Mim Capacitor And Method For Its Fabrication

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US Patent:
6885056, Apr 26, 2005
Filed:
Oct 22, 2003
Appl. No.:
10/692431
Inventors:
Dieter Dornisch - Carlsbad CA, US
David J Howard - Irvine CA, US
Abhijit B Joshi - Ladera Ranch CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L027/108
H01L029/76
H01L029/94
H01L031/119
US Classification:
257310, 257303, 257304, 257311, 438239, 438240, 438253
Abstract:
According to one exemplary embodiment, a high-k dielectric stack situated between upper and lower electrodes of a MIM capacitor comprises a first high-k dielectric layer, where the first high-k dielectric layer has a first dielectric constant. The high-k dielectric stack further comprises an intermediate dielectric layer situated on the first high-k dielectric layer, where the intermediate dielectric layer has a second dielectric constant. According to this exemplary embodiment, the high-k dielectric stack further comprises a second high-k dielectric layer situated on the intermediate dielectric layer, where the second high-k dielectric layer has a third dielectric constant. The second dielectric constant can be lower than the first dielectric constant and the third dielectric constant. The high-k dielectric stack further comprises first and second cladding layers, where the first cladding layer is situated underneath the first high-k dielectric layer and the second cladding layer is situated on the second high-k dielectric layer.

Method For Patterning Densely Packed Metal Segments In A Semiconductor Die And Related Structure

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US Patent:
6919272, Jul 19, 2005
Filed:
Feb 1, 2003
Appl. No.:
10/356447
Inventors:
Tinghao F. Wang - Irvine CA, US
Dieter Dornisch - Carlsbad CA, US
Julia M. Wu - Las Flores CA, US
Hadi Abdul-Ridha - Irvine CA, US
David J. Howard - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L021/44
US Classification:
438669, 438671, 438712, 438720, 438942, 438945
Abstract:
A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Densely Packed Metal Segments Patterned In A Semiconductor Die

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US Patent:
7709949, May 4, 2010
Filed:
Apr 22, 2005
Appl. No.:
11/112194
Inventors:
Tinghao F. Wang - Irvine CA, US
Dieter Dornisch - Carlsbad CA, US
Julia M. Wu - Las Flores CA, US
Hadi Abdul-Ridha - Irvine CA, US
David J. Howard - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 23/48
US Classification:
257704, 257750, 257752, 257758, 257E21311, 257E21589
Abstract:
A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region.

Deep Trench Isolation And Method For Forming Same

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US Patent:
7772673, Aug 10, 2010
Filed:
Mar 16, 2007
Appl. No.:
11/724916
Inventors:
Kevin Q. Yin - Irvine CA, US
Amol Kalburge - Irvine CA, US
David J. Howard - Irvine CA, US
Arjun Kar-Roy - Irvine CA, US
Dieter Dornisch - Carlsbad CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/04
US Classification:
257510, 257520, 257E27001
Abstract:
According to one exemplary embodiment, a semiconductor die including at least one deep trench isolation region for isolating an electronic device (for example, a bipolar device) includes a trench situated in a substrate of the semiconductor die, where the trench has sides surrounding the electronic device, and where the trench has at least one trench chamfered corner formed between and connecting the sides of the trench. The at least one trench chamferred corner is formed between a chamfered corner of an outside wall of said trench and a corner of an inside wall of the trench. A trench corner width at the at least one trench chamfered corner is less than a trench side width along the sides of the trench.

Method For Fabricating A Mim Capacitor Having Increased Capacitance Density And Related Structure

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US Patent:
7268038, Sep 11, 2007
Filed:
Nov 23, 2004
Appl. No.:
10/997638
Inventors:
Dieter Dornisch - Carlsbad CA, US
Kenneth M. Ring - Tustin CA, US
Tinghao F. Wang - Irvine CA, US
David Howard - Irvine CA, US
Guangming Li - Irvine CA, US
Assignee:
Newport Fab, LLC - Newport Beach CA
International Classification:
H01L 21/8242
US Classification:
438250, 257303, 257E21351, 438240, 438396
Abstract:
According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12. 5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2. 0 fF/um.

Separation And Purification Of Fluoride From Industrial Wastes

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US Patent:
58766855, Mar 2, 1999
Filed:
Sep 11, 1996
Appl. No.:
8/707907
Inventors:
Gerald A. Krulik - San Clemente CA
John A. Adams - Escondido CA
Dieter Dornisch - Oceanside CA
David W. Persichini - State College CA
Christopher S. Blatt - La Costa CA
Assignee:
IPEC Clean, Inc. - Oceanside CA
International Classification:
C01B 719
US Classification:
423488
Abstract:
A method for the removal and purification of substantially all of the fluoride ions contained in a solution containing greater than 10 parts per million (ppm) fluoride ion, a mixture of other anions, silicon in the form of a fluorosilicic acid, silicic acid, silicates, or silicon tetrafluoride, and optionally also containing complex metal fluorides, to produce an ultrapure hydrofluoric acid, comprising the steps of (a) adjusting the pH of the solution to an alkaline pH to hydrolyze the fluorosilicic acid and any complex metal fluorides; (b) removing the fluoride ions and other anions from the solution by passing the solution through an ion exchange resin, where the ion exchange resin is adapted to adsorb substantially all of the fluoride passed over the ion exchange resin; (c) displacing the fluoride ions and other anions bound to the ion exchange resin, thereby forming a mixture of anions in an effluent emanating from resin; (d) optionally concentrating the effluent at a high pH and then lowering the pH; and (e) distilling the mixture of anions in the effluent from a sulfuric acid solution to generate ultrapure hydrofluoric acid. An apparatus useful for practicing the method is also disclosed.

Methods For Barrier Layer Formation

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US Patent:
62551922, Jul 3, 2001
Filed:
Sep 29, 1998
Appl. No.:
9/163135
Inventors:
Dieter Dornisch - Carlsbad CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
H01L 2176
US Classification:
438430
Abstract:
An improved microelectronic device and methods for forming the device are disclosed. The device includes a conductive feature formed on a semiconductor wafer by creating a trench within an insulating material, depositing barrier material substantially only within the trench, depositing conductive material on the wafer surface and within the trench, and removing the conductive material from the wafer surface. Alternately, the barrier material may be deposited onto the wafer surface and the trench and removed from the wafer surface prior to conductive material deposition.
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Dieter D Dornisch from Carlsbad, CA, age ~64 Get Report