Resumes
Resumes
Chief Manager
View pageLocation:
Bellevue, WA
Industry:
Banking
Work:
Icici Bank Aug 29, 2010 - Aug 5, 2018
Internal Audit Manager
Idfc Bank Aug 29, 2010 - Aug 5, 2018
Chief Manager
Internal Audit Manager
Idfc Bank Aug 29, 2010 - Aug 5, 2018
Chief Manager
Education:
University of Mumbai 2001 - 2006
K.v.pendharkar College, Dombivli
K.v.pendharkar College, Dombivli
Skills:
Auditing
Senior Electrical Engineer
View pageLocation:
771 Fentress Blvd, Daytona Beach, FL 32114
Industry:
Computer Software
Work:
Smart Technologies Mar 1, 2015 - Jan 2017
System Validation Specialist at Smart Technologies
Ossia Inc. Mar 2012 - Nov 2012
Fpga Engineer
Mitcoe Pune India Jun 2003 - Dec 2010
Research Associate and Associate Professor
Vsoft Technology Aug 2001 - May 2003
Hardware Engineer
Microsoft Aug 2001 - May 2003
Senior Electrical Engineer
System Validation Specialist at Smart Technologies
Ossia Inc. Mar 2012 - Nov 2012
Fpga Engineer
Mitcoe Pune India Jun 2003 - Dec 2010
Research Associate and Associate Professor
Vsoft Technology Aug 2001 - May 2003
Hardware Engineer
Microsoft Aug 2001 - May 2003
Senior Electrical Engineer
Education:
Department of Technology, Savitribai Phule Pune University 2008 - 2014
Masters, Engineering Department of Technology, Savitribai Phule Pune University 1997 - 2000
Bachelor of Engineering, Bachelors, Electronics Engineering
Masters, Engineering Department of Technology, Savitribai Phule Pune University 1997 - 2000
Bachelor of Engineering, Bachelors, Electronics Engineering
Skills:
Vlsi
Testing
Vhdl
Fpga
Integrated Circuit Design
Asic
Simulations
C
Embedded Systems
Semiconductors
Hardware Architecture
Cmos
Digital Signal Processors
Circuit Design
Modelsim
Matlab
Analog
Firmware
Digital Electronics
Soc
Microcontrollers
Field Programmable Gate Arrays
Very Large Scale Integration
Microprocessors
Analog Design
Mixed Signal
Xilinx
Computer Architecture
Simulation
Ic
Dsp
Assembly
Rtl Design
Analog Circuit Design
Digital Design
Static Timing Analysis
Arm
Hardware Design
Testing
Vhdl
Fpga
Integrated Circuit Design
Asic
Simulations
C
Embedded Systems
Semiconductors
Hardware Architecture
Cmos
Digital Signal Processors
Circuit Design
Modelsim
Matlab
Analog
Firmware
Digital Electronics
Soc
Microcontrollers
Field Programmable Gate Arrays
Very Large Scale Integration
Microprocessors
Analog Design
Mixed Signal
Xilinx
Computer Architecture
Simulation
Ic
Dsp
Assembly
Rtl Design
Analog Circuit Design
Digital Design
Static Timing Analysis
Arm
Hardware Design
Languages:
English
Hindi
Marathi
Hindi
Marathi
Deepali Sane Bellevue, WA
View pageWork:
Omnilectric,Inc
Mar 2012 to 2000
FPGA Design Engineer
Mitcoe
Jul 2003 to 2000
Research Associate
V-Soft Consultancy Pvt. Ltd
Jul 2001 to Jun 2003
Hardware Design Engineer
Mar 2012 to 2000
FPGA Design Engineer
Mitcoe
Jul 2003 to 2000
Research Associate
V-Soft Consultancy Pvt. Ltd
Jul 2001 to Jun 2003
Hardware Design Engineer
Education:
Maharashtra Institute of Technology
Pune, Maharashtra
Jan 2008 to Jan 2011
master in EMBEDDED AND VLSI SYSYTEM DESIGN
Pune University
2000
Bachelor of engineering in ELECTRONICS AND COMMUNICATION
Government Polytechnic
1997
Diploma in Electronics & Telecommunication
Pune, Maharashtra
Jan 2008 to Jan 2011
master in EMBEDDED AND VLSI SYSYTEM DESIGN
Pune University
2000
Bachelor of engineering in ELECTRONICS AND COMMUNICATION
Government Polytechnic
1997
Diploma in Electronics & Telecommunication
Skills:
Programming Language: C, MATLAB (DSP tool), MULTISIM,Assembly Languages: 8085, 80X86, 80C51, 80C52,PIC24 Family, LPC2292/94,ARM7,HDL Languages: VHDL, Verilog,Operating system: Windows 98/2000/XP,Xilinx Project Navigator, Modelsim, Leonardo Spectrum, OrCAD