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Deepak M Pabari

from San Jose, CA
Age ~60
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Related to:
Priyanka Pabari, 26Meenal D Pabari, 59
Connected to:
Cedric L Pabarue, 80Cyd V Pabatao, 34Chandra S Pabba, 55Prasad V Pabbati, 62Meleta J Pabel, 76Joan E Pabelico, 56Kenneth J Pabelick, 65Jazmyn S Pabellon, 38Yamil X Pabellon, 51Adam G Paben, 40

Deepak Pabari Phones & Addresses

  • 5506 Cooney Pl, San Jose, CA 95123 (408) 439-9617
  • 444 Saratoga Ave, Santa Clara, CA 95050 (408) 984-4915
  • 901 Ashland Ave, Chicago, IL 60607 (312) 666-7570
  • 5506 Cooney Pl, San Jose, CA 95123

Work

Company: Xilinx 2003 to 2014 Position: Principal engineer

Education

Degree: Bachelors School / High School: University of Bombay Specialities: Electronics Engineering, Electronics

Skills

Fpga • Verilog • Xilinx • Eda • Simulations • Asic • Perl • Hardware Architecture • Software Development • Testing • C++ • Semiconductors • Digital Signal Processors • Debugging • Simulation • Modeling

Emails

d***[email protected]

Industries

Semiconductors

Resumes

Resumes

Deepak Pabari Photo 1

Senior Principal Engineer

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Xilinx 2003 - 2014
Principal Engineer
Microsemi Corporation 2003 - 2014
Senior Principal Engineer
Chameleon 1999 - 2003
Senior Staff Engineer
Frontline Design Automation 1994 - 1999
Project Lead
Cadence Design Systems 1991 - 1994
Staff Engineer
Education:
University of Bombay
Bachelors, Electronics Engineering, Electronics The University of Texas at Austin
Master of Science, Masters, Computer Engineering
Skills:
Fpga
Verilog
Xilinx
Eda
Simulations
Asic
Perl
Hardware Architecture
Software Development
Testing
C++
Semiconductors
Digital Signal Processors
Debugging
Simulation
Modeling

Business Records

Name / Title
Company / Classification
Phones & Addresses
Deepak Pabari
President
DESKTOP SOFTWARE PRODUCTS, INC
Custom Computer Programing
141 Saratoga Ave #1311, Santa Clara, CA 95051

Publications

Us Patents

Measuring Bridge-Fault Coverage For Test Patterns Within Integrated Circuits

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US Patent:
8001438, Aug 16, 2011
Filed:
Aug 15, 2008
Appl. No.:
12/192741
Inventors:
Deepak M. Pabari - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/28
G01R 27/28
G01R 31/00
G01R 31/14
G01R 31/08
G01R 31/02
G06F 11/00
G06F 17/50
G06F 9/455
G06F 11/22
G11C 7/00
G11C 29/00
US Classification:
714741, 714724, 702117, 365201, 703 14, 716104, 716106, 716136, 716115, 324526, 324537
Abstract:
A computer-implemented method of measuring bridge fault coverage for a test pattern for a circuit design to be implemented within a programmable logic device can include identifying simulation results and stuck at coverage of the circuit design for the test pattern (). Pairs of nets in the circuit design that are adjacent can be identified (). Each type of bridge fault for which each pair is tested can be determined according to the simulation results (). A measure of bridge fault coverage for the test pattern can be calculated according to which types of bridge faults each pair is tested and which net of each pair acts as an aggressor for each type of bridge fault tested (). The measure of bridge fault coverage can be output ().

Method Of Testing Circuit Blocks Of A Programmable Logic Device

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US Patent:
7430697, Sep 30, 2008
Filed:
Jul 21, 2005
Appl. No.:
11/186373
Inventors:
Deepak M. Pabari - San Jose CA, US
Assignee:
XILINX, Inc. - San Jose CA
International Classification:
G01R 31/28
US Classification:
714724, 702119, 716 4, 714727, 714725, 714726, 326 38, 326 39, 326 41, 326 40
Abstract:
A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit; routing the test signal source to the logic circuit; and determining if the logic circuit is defective. According to an alternate embodiment, a method enables re-routing a path from a shift register to a lookup table to determine whether a lookup table is defective. According to a further alternate embodiment, a method enables localized routing to reduce the probability that a defect is a result of a routing defect.
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Deepak M Pabari from San Jose, CA, age ~60 Get Report