Davide Mantegazza

20210151672, May 20, 2021

Nov 19, 2019

16/688309

- Santa Clara CA, US
DAVIDE MANTEGAZZA - Palo Alto CA, US
JOHN GORMAN - San Jose CA, US
INIYAN SOUNDAPPA ELANGO - Lehi UT, US
DAVIDE FUGAZZA - San Jose CA, US
ANDREA REDAELLI - Milano, IT
FABIO PELLIZZER - Boise ID, US

INTEL CORPORATION - Santa Clara CA

H01L 45/00
H01L 27/24

A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

20210098034, Apr 1, 2021

Sep 26, 2019

16/584339

- Santa Clara CA, US
Davide MANTEGAZZA - Palo Alto CA, US

G11C 7/10
G11C 8/08
G11C 7/12
G11C 8/10

Examples may include techniques to improve a read operation to a memory array. Examples include identifying characteristics of memory cells in the memory array such as relative positions of memory cells within the memory array and then set multiple read reference voltages or currents to detect a memory state of memory cells based on identified characteristics.

20200159424, May 21, 2020

Jan 24, 2020

16/751863

- Santa Clara CA, US
Prashant DAMLE - Portland OR, US
Davide MANTEGAZZA - Palo Alto CA, US

G06F 3/06

Deck offset techniques for multi-deck non-volatile memory can reduce the average raw bit error rate (RBER) for a memory system. Deck offset can enable accessing different physical decks for the same input deck address. In one example in a system with multiple memory components, different physical decks are accessed across multiple memory components for the same logical deck address. In one example in a system with one memory component, different physical decks are accessed across multiple partitions of the same memory component.

20150055407, Feb 26, 2015

Aug 26, 2013

14/010417

Davide Mantegazza - Palo Alto CA, US
Kiran Pangal - Fremont CA, US
Gerard H. Joyce - Folsom CA, US
Prashant Damle - Portland OR, US
Derchang Kau - Cupertino CA, US
Davide Fugazza - Sunnyvale CA, US

G11C 13/00

365163

Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In an embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device, wherein the memory cell is coupled with a capacitor and subsequent to said increasing the current, generating a transient current through the memory cell by discharge of the capacitor to reset the memory cell. In another embodiment, a method includes increasing a current through a memory cell of a phase change memory (PCM) device and controlling the current to be greater than a threshold current and lower than a hold current of the memory cell to set the memory cell. Other embodiments may be described and/or claimed.