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David C Uliana

from Austin, TX
Age ~34
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Also known as:
David Christopher Uliana, Dave Uliana, Liaina U David
Phone and address:
4514 Highland Ter, Austin, TX 78731
Related to:
Elizabeth V Brickhouse, 60Julie Bostic, 41Joshua Smith, 45Gertrude DaltonDennis G Smith, 71Ryan Elliott
Connected to:
Laura J Uliana, 64Danielle M Uliano, 30Joseph R Uliano, 49Michael Uliano, 40Kristy M Uliasz, 41Amanda A Uliaszek, 42Alyssa R Ulibarri, 31Deborah F Ulibarri, 69Isaac J Ulibarri, 51Juliann M Ulibarri, 45

David Uliana Phones & Addresses

  • 4514 Highland Ter, Austin, TX 78731
  • Christiansburg, VA
  • 1208 University Ter APT G, Blacksburg, VA 24060
  • 3204 Oak Ridge Rd SW, Roanoke, VA 24018 (540) 774-1985

Emails

c***[email protected]

Resumes

Resumes

David Uliana Photo 1

Software Engineer

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Location:
2640 west 45Th St, Austin, TX 78731
Industry:
Oil & Energy
Work:
Configurable Computing Lab, Virginia Tech - Blacksburg, Virginia since Aug 2011
Graduate Research Assistant
Information Sciences Institute - Arlington, Virginia May 2011 - Aug 2011
Visiting Research Assistant
E-Textiles Research Lab, Virginia Tech - Blacksburg, Virginia May 2010 - May 2011
Undergraduate Researcher
SiteVision, Inc. - Roanoke, Virginia May 2009 - Jan 2010
Web Applications Developer
TMEIC - Roanoke, Virginia May 2008 - Jan 2009
IT Intern
Education:
Virginia Tech 2011
Masters (M.S.) (in progress), Computer Engineering Virginia Tech 2008 - 2011
Bachelor of Science (B.S.), Computer Engineering Virginia Western Community College 2006 - 2008
Skills:
Fpga
C++
Matlab
Xilinx
Python
Simulations
Verilog
High Performance Computing
Embedded Systems
Hardware Architecture
Algorithms
Linux
Computer Architecture
Javascript
Jquery
Modelsim
Software Engineering
Labview
Eda
C#
Field Programmable Gate Arrays
Latex
Amazon Web Services
Html
Css
Heroku
Interests:
Guitar
Church Related Activities
Et Al
Motorcycles
Photography
Music
Languages:
English
David Uliana Photo 2

Graduate Student At Virginia Tech

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Position:
Graduate Research Assistant at Configurable Computing Lab, Virginia Tech
Location:
Blacksburg, Virginia
Industry:
Computer Hardware
Work:
Configurable Computing Lab, Virginia Tech - Blacksburg, Virginia since Aug 2011
Graduate Research Assistant
Information Sciences Institute - Arlington, Virginia May 2011 - Aug 2011
Visiting Research Assistant
E-Textiles Research Lab, Virginia Tech - Blacksburg, Virginia May 2010 - May 2011
Undergraduate Researcher
SiteVision, Inc. - Roanoke, Virginia May 2009 - Jan 2010
Web Applications Developer
TMEIC - Roanoke, Virginia May 2008 - Jan 2009
IT Intern
Education:
Virginia Tech 2011
Masters (M.S.) (in progress), Computer Engineering Virginia Tech 2008 - 2011
Bachelor of Science (B.S.), Computer Engineering Virginia Western Community College 2006 - 2008
Skills:
Matlab
FPGA
C++
Verilog
Xilinx
Python
JavaScript
jQuery
ModelSim
Interests:
Music, guitar, photography, motorcycles, church-related activities, et al.
Honor & Awards:
Bradley Fellowship

Publications

Us Patents

Value Transfer Between Program Variables Using Dynamic Memory Resource Mapping

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US Patent:
20170131984, May 11, 2017
Filed:
Nov 11, 2015
Appl. No.:
14/938649
Inventors:
- Austin TX, US
Tai A. Ly - Austin TX, US
David C. Uliana - Austin TX, US
Adam T. Arnesen - Pflugerville TX, US
Newton G. Petersen - Emporia KS, US
International Classification:
G06F 9/45
Abstract:
System and method for creating a program. A program may be compiled, including determining one or more value transfer operations in the program. Each value transfer operation may specify a value transfer between a respective one or more source variables and a destination variable. For each of the one or more value transfer operations, the value transfer operation may be implemented, where the implementation of the value transfer operation may be executable to assign each variable of the value transfer operation to a respective memory resource, thereby mapping the variables to the memory resources, and dynamically change the mapping, including assigning the destination variable to the memory resource of a first source variable of the one or more source variables, thereby transferring the value from the first source variable to the destination variable without copying the value between the memory resources.

Self-Addressing Memory

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US Patent:
20170115885, Apr 27, 2017
Filed:
Jan 3, 2017
Appl. No.:
15/397107
Inventors:
- Austin TX, US
Swapnil D. Mhaske - Highland Park NJ, US
Hojin Kee - Austin TX, US
Adam T. Arnesen - Pflugerville TX, US
David C. Uliana - Austin TX, US
Newton G. Petersen - Emporia KS, US
International Classification:
G06F 3/06
H03M 13/00
H03M 13/11
Abstract:
Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

Self-Addressing Memory

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US Patent:
20160070485, Mar 10, 2016
Filed:
Oct 24, 2014
Appl. No.:
14/523413
Inventors:
- Austin TX, US
Swapnil D. Mhaske - Highland Park NJ, US
Hojin Kee - Austin TX, US
Adam T. Arnesen - Pflugerville TX, US
David C. Uliana - Austin TX, US
Newton G. Petersen - Emporia KS, US
International Classification:
G06F 3/06
H03M 13/11
Abstract:
Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

Memory System Configured To Avoid Memory Access Hazards For Ldpc Decoding

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US Patent:
20160070498, Mar 10, 2016
Filed:
Oct 24, 2014
Appl. No.:
14/522869
Inventors:
- Austin TX, US
Swapnil D. Mhaske - Highland Park NJ, US
Hojin Kee - Austin TX, US
Adam T. Arnesen - Pflugerville TX, US
David C. Uliana - Austin TX, US
Newton G. Petersen - Emporia KS, US
International Classification:
G06F 3/06
H03M 13/11
G06F 11/10
Abstract:
Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.

Configuring Circuitry With Memory Access Constraints For A Program

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US Patent:
20160070499, Mar 10, 2016
Filed:
Oct 24, 2014
Appl. No.:
14/523039
Inventors:
- Austin TX, US
Swapnil D. Mhaske - Highland Park NJ, US
Hojin Kee - Austin TX, US
Adam T. Arnesen - Pflugerville TX, US
David C. Uliana - Austin TX, US
Newton G. Petersen - Emporia KS, US
International Classification:
G06F 3/06
H03M 13/11
Abstract:
Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.

Reordering A Sequence Of Memory Accesses To Improve Pipelined Performance

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US Patent:
20160070662, Mar 10, 2016
Filed:
Oct 24, 2014
Appl. No.:
14/523232
Inventors:
- Austin TX, US
Swapnil D. Mhaske - Highland Park NJ, US
Hojin Kee - Austin TX, US
Adam T. Arnesen - Pflugerville TX, US
David C. Uliana - Austin TX, US
Newton G. Petersen - Emporia KS, US
International Classification:
G06F 13/16
G11C 7/10
Abstract:
Techniques are disclosed relating to reordering sequences of memory accesses. In one embodiment, a method includes storing a specified sequence of memory accesses that corresponds to a function to be performed. In this embodiment, the specified sequence of memory accesses has first memory access constraints. In this embodiment, the method further includes reordering the specified sequence of memory accesses to create a reordered sequence of memory accesses that has second, different memory access constraints. In this embodiment, the reordered sequence of memory accesses is usable to access a memory to perform the function. In some embodiments, performance estimates are determined for a plurality of reordered sequences of memory accesses, and one of the reordered sequences is selected based on the performance estimates. In some embodiments, the reordered sequence is used to compile a program usable to perform the function.
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David C Uliana from Austin, TX, age ~34 Get Report