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David Onsongo Phones & Addresses

  • Dripping Springs, TX
  • Austin, TX
  • 11725 Voelker Reinhardt Way, Manor, TX 78653 (845) 565-0445
  • Pflugerville, TX
  • 7604 Fair Oaks Ave #1033, Dallas, TX 75231 (214) 272-2264
  • 8499 Greenville Ave #205, Dallas, TX 75231 (214) 272-2264
  • 9655 Chimney Hill Ln, Dallas, TX 75243 (972) 238-7549
  • 9655 Chimney Hill Ln #2130, Dallas, TX 75243 (972) 238-7549
  • Rochester, MN
  • Byron, MN
  • Newburgh, NY

Work

Company: Ibm May 2006 Position: Analog designer & technologist

Education

School / High School: The University of Texas at Austin- Austin, TX 2003 Specialities: PhD in Electrical Engineering

Resumes

Resumes

David Onsongo Photo 1

David Onsongo Manor, TX

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Work:
IBM

May 2006 to 2000
Analog Designer & Technologist

IBM
Hopewell Junction, NY
Oct 2003 to Apr 2006
Device Designer

University of Texas at Austin
Austin, TX
Jan 1999 to Oct 2003
Research Assistant

IBM
Hopewell Junction, NY
May 2002 to Aug 2002
Intern

Motorola
Austin, TX
Jun 2000 to Aug 2000
Intern

TestChip Technologies
Dallas, TX
Feb 1997 to Dec 1998
Member of Technical Staff

Education:
The University of Texas at Austin
Austin, TX
2003
PhD in Electrical Engineering

The University of Texas at Austin
Austin, TX
2000
MS in Electrical Engineering

The University of Texas at Austin
Austin, TX
1996
BS in Electrical Engineering

Business Records

Name / Title
Company / Classification
Phones & Addresses
David Onsongo
Director
HAZINA INVESTMENT MANAGEMENT LLC
3317 Finley Rd, Irving, TX 75062
10900 Stonelake Blvd STE A 320, Austin, TX 78759
David Onsongo
Manager
AFRICA DEVELOPMENT LINK LIMITED COMPANY
Business Services at Non-Commercial Site · Nonclassifiable Establishments
937 Buffalo Spg Dr, Fort Worth, TX 76140
4004 Sprucebark Dr, Keller, TX 76244
PO Box 818, Keene, TX 76059

Publications

Us Patents

Structure And Method For Forming A Light Detecting Diode And A Light Emitting Diode On A Silicon-On-Insulator Wafer Backside

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US Patent:
8354678, Jan 15, 2013
Filed:
Jul 11, 2011
Appl. No.:
13/179948
Inventors:
Benjamin A. Fox - Rochester MN, US
Nathaniel J. Gibbs - Iowa City IA, US
Andrew B. Maki - Rochester MN, US
David M. Onsongo - Austin TX, US
Trevor J. Timpane - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/15
US Classification:
257 77, 257287, 257292, 257E29313, 257E21447
Abstract:
A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Calibrating On-Chip Resistors Via A Daisy Chain Scheme

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US Patent:
8451021, May 28, 2013
Filed:
May 10, 2012
Appl. No.:
13/468301
Inventors:
Benjamin A. Fox - Rochester MN, US
Nathaniel J. Gibbs - Iowa City IA, US
Andrew B. Maki - Rochester MN, US
David M. Onsongo - Manor TX, US
Trevor J. Timpane - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03K 19/003
US Classification:
326 30, 326 21
Abstract:
A method for calibrating resistors on an integrated circuit chip via a daisy chain scheme. The method comprises the step of configuring one or more links of the daisy chain scheme, wherein each of the one or more links comprises one or more master resistors and one or more slave resistors. The method further comprises the steps of calibrating at least one on-chip reference resistor, the one or more master resistors, and the one or more slave resistors via the daisy chain scheme. The method using the daisy chain scheme enables resistance of at least one off-chip reference resistor to be duplicated to multiple distant locations while maintaining a low mismatch error.

Heat Source Integration For Electromigration Analysis

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US Patent:
20170103146, Apr 13, 2017
Filed:
Oct 7, 2015
Appl. No.:
14/877189
Inventors:
- Armonk NY, US
James M. Johnson - Milton VT, US
David M. Onsongo - Manor TX, US
International Classification:
G06F 17/50
Abstract:
A computer-implemented method includes receiving layout information associated with a circuit design at an extractor, and generating three-dimensional (3-D) heat source grid information based on the layout information, an extracted netlist, and wire information. The method also includes sending the wire information to an electromigration(EM)/current(IR) analyzer, sending the extracted netlist to a circuit simulator, and sending the 3-D heat source grid information to a thermal analysis component. The circuit simulator is configured to generate temperature waveforms and current waveforms based on the extracted netlist. The thermal analysis component is configured to generate heat source information to be provided to the EM/IR analyzer. The method further includes determining, at the EM/IR analyzer, an electromigration risk associated with a wire based on the wire information, the current waveforms, and the heat source information.
David M Onsongo from Dripping Springs, TX, age ~52 Get Report