Darin J Daudelin

6731134, May 4, 2004

Mar 31, 2003

10/249311

William L. Bucossi - Burlington VT
Bret R. Dale - Burlington VT
Darin J. Daudelin - Essex Junction VT

International Business Machines Corporation - Armonk NY

H03K 1902

326 56, 326 27, 326121

A driver including boost circuitry for reducing tri-state delay. Boost circuitry includes boost legs ( ) and ( ) having boost delay chains ( ) and ( ), respectively. Subcircuits ( ) and ( ) may include a series of inverters or other devices to delay a tri-state enable signal (EN ) or (EN BAR) for a predetermined amount of time substantially equivalent to the time it takes for a first signal (A ) to travel from input pin A to PAD. Transient current provides a boost by discharging or charging output nodes (G ) and (G ), respectively. Boost legs ( ) and ( ) remain on for the length of time it takes for enable signal (EN ) or (EN BAR) to travel through subcircuits ( ) and ( ). The boost increases the rate of transition of output nodes (G ) and (G ) thereby reducing the delay of tri-state signal (EN ).

7282961, Oct 16, 2007

Apr 13, 2006

11/279658

Darin Daudelin - Williston VT, US
Michael J. Lencioni - Austin TX, US

International Business Machines Corporation - Armonk NY

H03K 19/094
H03K 19/20

326121, 326 83, 326 86, 326 87, 326112, 327112

A process compensation circuit for an inverting element of a CMOS device, including a duplicate inverting element connected in parallel with the inverting element of the CMOS device. An upside-down inverter stage has an input connected to the output of the duplicate inverting element, and an output connected to the output of the inverting element of the CMOS device. The upside-down inverter stage is configured to counteract a delayed logic transition of the output of the inverting element of the CMOS device in the event of a process skew between NFET and PFET devices.

7474124, Jan 6, 2009

Mar 12, 2007

11/684890

Bret R. Dale - Jericho VT, US
Darin J. Daudelin - Williston VT, US
Todd M. Fisher - Essex Junction VT, US
Douglas W. Stout - Milton VT, US

International Business Machines Corporation - Armonk NY

H03K 17/16

326 82, 326 30

The inventions herein are directed to an inventive bus keeper and logic circuit for use with an I/O circuit, for example, for use on the receiver side of the I/O buffer circuit. The inventive circuit connects one data line of an IC function to one line of a tri-state bus (one bit of data per bus line or wire). The bus keeper and logic control circuit is maintained in isolation from I/O functional driver and is responsive to a tri-state signal (TS), normally provided by the IC or SOC, or the I/O circuit during normal I/O receiver side operation. The inventive bus keeper and logic circuit selectively enables any of a tri-state state, a pull-up state, pull-down state and bus keep mode state at the driver output pad in the presence of the tri-state enable signal, and is disabled when the I/O bus drive buffer circuit is in drive mode.

7622972, Nov 24, 2009

Feb 5, 2008

12/025786

Bret Roberts Dale - Jericho VT, US
Darin James Daudelin - Williston VT, US
Ryan Andrew Jurasek - S. Burlington VT, US
Dave Eugene Chapmen - Shelburne VT, US

Nanya Technology Corp. - Kueishan, Tao-Yuan Hsien

H03K 5/12

327170, 327134

A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled by a comparison signal; a signal conversion circuit, coupled to the adjustable capacitive component, for restoring charges stored in the adjustable capacitive component to a predetermined value when a voltage level of the output signal reaches a reference value to generate a clock-like signal; and a comparison circuit, coupled to the signal conversion circuit and the adjustable capacitive component, for comparing a period of the clock-like signal with a reference period of a reference clock signal and generating the comparison signal to adjust the total capacitance of the adjustable capacitive component when periods are not the same.

7633331, Dec 15, 2009

Mar 18, 2008

12/050178

Ryan Andrew Jurasek - S. Burlington VT, US
Bret Roberts Dale - Jericho VT, US
Darin James Daudelin - Williston VT, US
Dave Eugene Chapmen - Shelburne VT, US

Nanya Technology Corp. - Kueishan, Tao-Yuan Hsien

G05F 1/10

327536, 363 59

A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.

7663418, Feb 16, 2010

Jan 3, 2008

11/969209

Bret Roberts Dale - Jericho VT, US
Ryan Andrew Jurasek - S. Burlington VT, US
Darin James Daudelin - Williston VT, US
Dave Eugene Chapmen - Shelburne VT, US

Nanya Technology Corp. - Kuelshan, Tao-Yuan Hsien

H03K 5/12

327170, 327108

An apparatus for compensating slew rate of a driving circuit includes: a first circuit, for receiving an edge transition from the driving circuit and generating a first pulse proportional to an actual slope of the edge transition; a second circuit, for receiving an ideal edge transition of the driving circuit and generating a second pulse proportional to an ideal slope of the ideal edge transition; a comparison circuit, coupled to the first circuit and the second circuit, for comparing an extreme value of amplitude of the first pulse with an extreme value of amplitude of the second pulse to produce a comparison signal; and a control circuit, coupled to the comparison circuit, for increasing or decreasing the slew rate of the driving circuit according to the comparison signal.

7750684, Jul 6, 2010

Apr 18, 2008

12/105280

Ryan Andrew Jurasek - S. Burlington VT, US
Bret Roberts Dale - Jericho VT, US
Darin James Daudelin - Williston VT, US
Dave Eugene Chapmen - Shelburne VT, US

Nanya Technology Corp. - Kueishan, Tao-Yuan Hsien

G01R 23/02
H03D 3/00
H03K 9/06

327 47, 327143, 327198

A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.

7863883, Jan 4, 2011

Apr 18, 2008

12/105276

Ryan Andrew Jurasek - S. Burlington VT, US
Bret Roberts Dale - Jericho VT, US
Darin James Daudelin - Williston VT, US
Dave Eugene Chapmen - Shelburne VT, US

Nanya Technology Corp. - Kueishan, Tao-Yuan Hsien

G05F 3/16
G05F 3/20

323313, 323901, 323312

A low-voltage current reference providing a current being substantially constant with temperature includes a low voltage bandgap, a start circuit coupled to the low voltage bandgap, and a current summer coupled to the low voltage bandgap and to the start circuit. The low voltage bandgap is for providing a constant voltage reference, and the start circuit is for starting the low voltage bandgap from a non-start mode and for providing a proportional to absolute temperature (PTAT) current reference. The current summer is for providing a constant current reference according to the constant voltage reference and the PTAT current reference.