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Daniel M Boyne

from Austin, TX
Age ~58

Daniel Boyne Phones & Addresses

  • 6609 Aden Ln, Austin, TX 78739 (512) 288-2484
  • 12001 Sky West Dr W, Austin, TX 78758 (512) 336-7599 (512) 836-7599
  • Columbus, OH
  • Wappingers Falls, NY
  • 6609 Aden Ln, Austin, TX 78739

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: Bachelor's degree or higher

Professional Records

License Records

Daniel Robert Boyne

Address:
449 E Tulane Rd, Columbus, OH 43202
License #:
12927 - Expired
Category:
Architecture

Daniel Robert Boyne

Address:
449 E Tulane Rd, Columbus, OH 43214
Phone:
(614) 653-7193
License #:
8255
Organization:
GreenbergFarrow

Daniel Robert Boyne

Address:
449 E Tulane Rd, Columbus, OH 43202
License #:
AR97135 - Active
Category:
Architect
Issued Date:
Jul 7, 2014
Effective Date:
Jul 7, 2014
Expiration Date:
Feb 28, 2019

Daniel R Boyne

Address:
Columbus, OH 43202
License #:
32111 - Active
Issued Date:
Sep 16, 2014
Expiration Date:
Aug 31, 2017
Type:
Architect

Daniel Robert Boyne

Address:
449 E Tulane Rd, Columbus, OH
License #:
24307 - Active
Category:
Architect
Issued Date:
Jul 29, 2014
Expiration Date:
Feb 28, 2018

Daniel R Boyne

Address:
Columbus, OH
License #:
21AI01975600 - Active
Category:
Architecture
Issued Date:
Oct 28, 2014
Expiration Date:
Jul 31, 2017
Type:
Registered Architect

Daniel R. Boyne

Address:
Columbus, OH 43214
License #:
6393 - Active
Category:
Architecture
Issued Date:
Jul 23, 2014
Expiration Date:
Dec 31, 2017

Daniel Robert Boyne

Address:
Columbus, OH 43202
License #:
RA407366 - Active
Category:
Architects
Type:
Registered Architect

Publications

Isbn (Books And Publications)

The Red Rose Crew: A True Story of Women, Winning, and the Water

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Author

Daniel J. Boyne

ISBN #

0786866225

The Red Rose Crew: A True Story of Women, Winning, and the Water

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Author

Daniel J. Boyne

ISBN #

0786889861

Us Patents

Self-Aligned, Lateral Diffusion Barrier In Metal Lines To Eliminate Electromigration

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US Patent:
6597067, Jul 22, 2003
Filed:
Apr 17, 1997
Appl. No.:
08/839843
Inventors:
Glenn Allen Biery - Poughkeepsie NY
Daniel Mark Boyne - Austin TX
Hormazdyar Minocher Dalal - Milton NY
H. Daniel Schnurmann - Monsey NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2348
US Classification:
257751, 257700, 257701, 257758, 257750, 257915, 257774, 257766, 257763, 257764, 257765, 257761
Abstract:
An interconnection wiring structure in an integrated circuit chip designed to eliminate electromigration. The structure includes segments of aluminum interspersed with segments of refractory metal, wherein each aluminum segment is followed by a segment of refractory metal. The aluminum and refractory metal segments are aligned with respect to each other to ensure electrical continuity and to force the electrical current to sequentially cross the aluminum and the refractory metal segments. The above structure can be advantageously enhanced by adding an underlayer, an overlayer or both, all of which are made of refractory metal. The interconnection wire structure described above can be expanded to include vias or studs linking interconnection lines placed at different levels of the IC chip.

Test Vehicles For Encapsulated Semiconductor Device Packages

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US Patent:
20130330846, Dec 12, 2013
Filed:
Jun 12, 2012
Appl. No.:
13/494160
Inventors:
Jinbang Tang - Chandler AZ, US
Daniel M. Boyne - Austin TX, US
International Classification:
H01L 21/66
G01R 31/26
US Classification:
438 15, 32475601, 257E21531
Abstract:
A mechanism to electrically evaluate signals within an encapsulated semiconductor device package without the need for redesigning the package substrate is provided. Test bond pads are provided on a top surface of a semiconductor device die being placed within the semiconductor device package. One or more wire bonds having an elevated loop height are formed on the test bond pads. After encapsulating the semiconductor device package, the package encapsulant is subject to a backgrind process to expose a portion of the test connection wire bonds. Only an amount of the package encapsulant sufficient to expose each test connection wire bond is removed, so that the remaining encapsulant will continue to have the same effect on the package as would be present in a production device. Test probes can then be applied to the exposed test connection wire bonds.

Dual Channel D.c. Low Noise Measurement System And Test Methodology

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US Patent:
55635172, Oct 8, 1996
Filed:
May 16, 1995
Appl. No.:
8/442556
Inventors:
Glenn A. Biery - Poughkeepsie NY
Daniel M. Boyne - Wappingers Falls NY
Kenneth P. Rodbell - Poughquag NY
Richard G. Smith - Poughkeepsie NY
Michael H. Wood - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 2926
US Classification:
324613
Abstract:
A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D. U. T. ). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.

Method Of Making Self-Aligned, Lateral Diffusion Barrier In Metal Lines To Eliminate Electromigration

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US Patent:
54707889, Nov 28, 1995
Filed:
Feb 28, 1994
Appl. No.:
8/203158
Inventors:
Glenn A. Biery - Poughkeepsie NY
Daniel M. Boyne - Austin TX
Hormazdyar M. Dalal - Milton NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21441
US Classification:
437190
Abstract:
A method of providing interconnections to a semiconductor integrated chip designed to eliminate electromigration. The method includes the steps of forming an interconnection with segments of Al interspersed with segments of a refractory metal, wherein each aluminum segments is followed by a segment of refractory metal, aligning the aluminum and refractory metal segments with respect to each other ensuring electrical continuity.

Dual Channel D.c. Low Noise Measurement System And Test Methodology

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US Patent:
54343852, Jul 18, 1995
Filed:
Nov 2, 1992
Appl. No.:
7/970370
Inventors:
Glenn A. Biery - Poughkeepsie NY
Daniel M. Boyne - Wappingers Falls NY
Kenneth P. Rodbell - Poughquag NY
Richard G. Smith - Poughkeepsie NY
Michael H. Wood - Hopewell Junction NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
F27D 1102
H05B 1100
H02H 704
US Classification:
219385
Abstract:
A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D. U. T. ). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.
Daniel M Boyne from Austin, TX, age ~58 Get Report