Inventors:
Rolf Hilgendorf - Boeblingen, DE
Jens Kuenzer - Leinfelden-Echterdingen, DE
Cédric Lichtenau - Boeblingen, DE
Thomas Pflueger - Leinfelden, DE
Mathew I. Ringler - Burlington VT, US
Gerard M. Salem - Essex Junction VT, US
Peter A. Sandon - Essex Junction VT, US
Dana J. Thygesen - Monkton VT, US
Ulrich Weiss - Holzgerlingen, DE
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H03L 7/00
Abstract:
A synchronization system capable of simultaneously resetting frequency divide-by counters () of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal ()) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit () for each processor that simulates in the undivided signal (Mclk/1 signal ()) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal () and sends an asynchronous offset signal () to a counter re-setter () that resets the divide-by counter to zero based on the offset signal.
