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Daewoong Suh

from Dublin, CA
Age ~55
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Also known as:
Dae Woong Suh, Dae W Suh, Dave Suh, Daewon Suh, G Suh
Related to:
Grace SuhHyo J Son, 50Son Y Yoon, 55
Connected to:
Ayra S Suh, 50Catherine R Suh, 44Changwon Suh, 54Cheol H Suh, 70Chul Suh, 54Cindy Suh, 43Claudio S Suh, 45Donny W Suh, 56Doris Y Suh, 31Duk J Suh, 67

Daewoong Suh Phones & Addresses

  • Dublin, CA
  • 16821 1St St, Phoenix, AZ 85045
  • 4920 Friar Ave, Fremont, CA 94555
  • 2022 Nevada St, Chandler, AZ 85225
  • Stanford, CA
  • Maricopa, AZ

Publications

Us Patents

Intermetallic Solder With Low Melting Point

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US Patent:
7224067, May 29, 2007
Filed:
Sep 15, 2005
Appl. No.:
11/229184
Inventors:
Daewoong Suh - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
US Classification:
257772, 2281805, 228 563
Abstract:
Embodiments of the invention provide a low-melting temperature comprised primarily of a bulk intermetallic phase material. This solder may allow reflow with less of a chance to damage microelectronic devices due to coefficient of thermal expansion mismatches, and may be creep resistant even at high homologous temperatures.

Stress-Relief Layer And Stress-Compensation Collar In Contact Arrays, And Processes Of Making Same

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US Patent:
7244634, Jul 17, 2007
Filed:
Mar 31, 2004
Appl. No.:
10/815968
Inventors:
Daewoong Suh - Phoenix AZ, US
Saikumar Jayaraman - Chandler AZ, US
Mohd Erwan P. Bin Basiron - Pulau Pinang, MY
Sheau Hooi Lim - Penang, MY
Yoong Tatt P. Chin - Penang, MY
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/00
US Classification:
438108, 438612, 257E21514
Abstract:
A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is mated and the SCC partially embeds the solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes a stress-relief layer and a stress-compensation collar is also included.

Stress-Relief Layers And Stress-Compensation Collars With Low-Temperature Solders For Board-Level Joints, And Processes Of Making Same

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US Patent:
7253088, Aug 7, 2007
Filed:
Sep 29, 2004
Appl. No.:
10/954999
Inventors:
Daewoong Suh - Phoenix AZ, US
Saikumar Jayaraman - Chandler AZ, US
Stephen E. Lehman - Chandler AZ, US
Mitesh Patel - Phoenix AZ, US
Tiffany A. Byrne - Chandler AZ, US
Edward L. Martin - Chandler AZ, US
Mohd Erwan B. Basiron - Pulau Pinang, MY
Wei Keat Loh - Penang, MY
Sheau Hooi Lim - Pulau Penang, MY
Yoong Tatt P. Chin - Penang, MY
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438612, 257E21508
Abstract:
A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Stress-Relief Layers And Stress-Compensation Collars With Low-Temperature Solders For Board-Level Joints, And Processes Of Making Same

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US Patent:
7291548, Nov 6, 2007
Filed:
Apr 17, 2007
Appl. No.:
11/736280
Inventors:
Daewoong Suh - Phoenix AZ, US
Saikumar Jayaraman - Chandler AZ, US
Stephen E. Lehman - Chandler AZ, US
Mitesh Patel - Phoenix AZ, US
Tiffany A. Byrne - Chandler AZ, US
Edward L. Martin - Chandler AZ, US
Mohd Erwan B. Basiron - Pulau Pinang, MY
Wei Keat Loh - Penang, MY
Sheau Hooi Lim - Penang, MY
Yoong Tatt P. Chin - Penang, MY
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438613, 438612
Abstract:
A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.

Soldering An Electronics Package To A Motherboard

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US Patent:
7357293, Apr 15, 2008
Filed:
Mar 24, 2004
Appl. No.:
10/808192
Inventors:
Daewoong Suh - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
B23K 31/02
US Classification:
22818021, 22818022, 228254
Abstract:
In some example embodiments, a method includes engaging a first contact on a motherboard with a second contact on an electronic package. A portion of one of the first and second contacts is covered with an interlayer that has a lower melting temperature than both of the first and second contacts. The method further includes bonding the first contact to the second contact by melting the interlayer to diffuse the interlayer into the first and second contacts. The bonded first and second contacts have a higher melting temperature than the interlayer before melting. In other example embodiments, an electronic assembly includes a motherboard having a first contact that is bonded to a second contact on an electronic package. An interlayer is diffused within the first and second contacts such that they have a higher melting temperature than the interlayer before the interlayer is diffused into the first and second contacts.

Nanostructure-Based Package Interconnect

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US Patent:
7371674, May 13, 2008
Filed:
Dec 22, 2005
Appl. No.:
11/315532
Inventors:
Daewoong Suh - Phoenix AZ, US
Nachiket R. Raravikar - Chandler AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438612, 257E5104, 257E21287, 257E21291, 977700, 977712, 977762
Abstract:
An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.

Microelectronic Package Interconnect And Method Of Fabrication Thereof

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US Patent:
7402909, Jul 22, 2008
Filed:
Apr 28, 2005
Appl. No.:
11/116537
Inventors:
Daewoong Suh - Phoenix AZ, US
Amram Eitan - Scottsdale AZ, US
Yongki Min - Phoenix AZ, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/48
H01L 23/52
US Classification:
257753, 977932
Abstract:
A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.

Sintered Metallic Thermal Interface Materials For Microelectronic Cooling Assemblies

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US Patent:
7535099, May 19, 2009
Filed:
Sep 26, 2006
Appl. No.:
11/528123
Inventors:
Daewoong Suh - Phoenix AZ, US
Chi-won Hwang - Tsukuba, JP
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/373
US Classification:
257713, 257712, 257E23112
Abstract:
A microelectronic cooling assembly and method for fabricating the same are described. In one example, a microelectronic cooling assembly includes a microelectronic device, a heat spreader, and a thermal interface material (TIM) that thermally joins the microelectronic device and heat spreader, the TIM comprising a sintered metallic nanopaste.
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Daewoong Suh from Dublin, CA, age ~55 Get Report