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Conrad H Ziesler

from Seattle, WA
Age ~47
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Also known as:
Conrad Havluj Ziesler, Havluj Ziesler Conrad, Ziesler Conrad, Conrad R
Phone and address:
6032 36Th Ave NE, Seattle, WA 98115
Related to:
Rachel A O'Meara, 49
Connected to:
Constance M Ziesman, 82Julie I Ziesman, 65Denise R Ziesmer, 58Edward Ziesmer, 44Frank Ziesmer, 78John J Ziesmer, 49Mark A Ziesmer, 53Teresa M Ziesmer, 66David D Ziessler, 69Mark E Ziessman, 77

Conrad Ziesler Phones & Addresses

  • 6032 36Th Ave NE, Seattle, WA 98115
  • 3624 Meridian Ave, Seattle, WA 98103 (206) 547-0325
  • W7425 Old 14 Rd, Ladysmith, WI 54848 (715) 532-3209
  • Granby, MA
  • Mountain View, CA
  • 20779 Locust Dr, Los Gatos, CA 95033
  • Ann Arbor, MI
  • Whitmore Lake, MI
  • 6032 36Th Ave NE, Seattle, WA 98115 (206) 547-0325

Work

Company: Apple Jul 2008 Position: Engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Michigan 1999 to 2004 Specialities: Electrical Engineering

Skills

Debugging • Embedded Systems • Asic • Soc • Semiconductors • Verilog • Ic • Vlsi • Hardware Architecture • Eda

Industries

Semiconductors

Resumes

Resumes

Conrad Ziesler Photo 1

Engineer

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Location:
Seattle, WA
Industry:
Semiconductors
Work:
Apple
Engineer
Pa Semi Jan 2006 - Jul 2008
Engineer
Multigig 2004 - 2006
Technical Staff
Education:
University of Michigan 1999 - 2004
Doctorates, Doctor of Philosophy, Electrical Engineering Caltech 1995 - 1999
Bachelors, Bachelor of Science, Electrical Engineering
Skills:
Debugging
Embedded Systems
Asic
Soc
Semiconductors
Verilog
Ic
Vlsi
Hardware Architecture
Eda

Publications

Us Patents

Energy Recovery Boost Logic

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US Patent:
7355454, Apr 8, 2008
Filed:
Jun 15, 2005
Appl. No.:
11/153135
Inventors:
Marios C. Papaefthymiou - Ann Arbor MI, US
Visvesh S. Sathe - Ann Arbor MI, US
Conrad H. Ziesler - Los Gatos CA, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
H03K 19/094
H03K 19/0175
US Classification:
326 93, 326 68, 326 98, 327109, 327333
Abstract:
A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.

Digital Frequency Synthesizer

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US Patent:
7782988, Aug 24, 2010
Filed:
May 2, 2005
Appl. No.:
11/121161
Inventors:
Conrad Havluj Ziesler - Seattle WA, US
Assignee:
Multigig Inc. - San Jose CA
International Classification:
H04L 7/02
H04L 7/00
US Classification:
375354, 375359, 375371, 375373
Abstract:
A system and method for synthesizing a frequency using a multi-phase oscillator. A state machine operating on one of the phases of the oscillator computes, based on a pair of input integers, a phase select vector that indicates when a particular phase of the multi-phase oscillator should be selected when a transition of the waveform of the output frequency is needed. The phase select vector is then re-timed to form a retimed phase vector so that each phase select signal is in phase with signal it is designed to select. The signals in the retimed phase vector then can be combined to create the output frequency directly or can be used to select the corresponding phase of the multi-phase oscillator, if more accuracy is desired. In one embodiment, the multi-phase oscillator is a rotary traveling wave oscillator which provides highly accurate multiple phases.

Clock Distribution Network Architecture With Clock Skew Management

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US Patent:
7956664, Jun 7, 2011
Filed:
Dec 3, 2007
Appl. No.:
11/949673
Inventors:
Jerry Kao - Ann Arbor MI, US
Visvesh Sathe - Fort Collins CO, US
Marios C. Papaefthymiou - Ann Arbor MI, US
Conrad Ziesler - Granby MA, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
H03K 3/00
US Classification:
327293, 327291, 327292, 327294
Abstract:
Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Temperature Compensation In Integrated Circuit

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US Patent:
8169764, May 1, 2012
Filed:
Feb 20, 2009
Appl. No.:
12/390085
Inventors:
Toshinari Takayanagi - San Jose CA, US
Conrad H. Ziesler - Seattle WA, US
Zongjian Chen - Palo Alto CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H02H 5/00
US Classification:
361103
Abstract:
In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.

Clock Distribution Network Architecture With Clock Skew Management

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US Patent:
8289063, Oct 16, 2012
Filed:
May 18, 2011
Appl. No.:
13/110439
Inventors:
Jerry Kao - Ann Arbor MI, US
Visvesh Sathe - Fort Collins CO, US
Marios C. Papaefthymiou - Ann Arbor MI, US
Conrad Ziesler - Granby MA, US
Assignee:
The Regents of the University of Michigan - Ann Arbor MI
International Classification:
H03K 3/013
US Classification:
327292, 327291, 327293, 327294
Abstract:
Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Power Switch Ramp Rate Control Using Daisy-Chained Flops

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US Patent:
8362805, Jan 29, 2013
Filed:
Feb 15, 2010
Appl. No.:
12/705834
Inventors:
Shingo Suzuki - San Jose CA, US
Vincent R. von Kaenel - Palo Alto CA, US
Toshinari Takayanagi - San Jose CA, US
Conrad H. Ziesler - Seattle WA, US
Daniel C. Murray - Morgan Hill CA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03K 193/00
H03B 21/00
US Classification:
326 93, 326 21, 326 95, 326 98, 327107, 327113, 327115
Abstract:
In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Power Switch Ramp Rate Control Using Programmable Connection To Switches

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US Patent:
8421499, Apr 16, 2013
Filed:
Feb 15, 2010
Appl. No.:
12/705837
Inventors:
Toshinari Takayanagi - San Jose CA, US
Shingo Suzuki - San Jose CA, US
Jung-Cheng Yeh - San Jose CA, US
Conrad H. Ziesler - Seattle WA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
H03K 19/23
US Classification:
326 33, 326 93, 326 95
Abstract:
In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.

Performing Stuck-At Testing Using Multiple Isolation Circuits

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US Patent:
8553488, Oct 8, 2013
Filed:
Jun 10, 2011
Appl. No.:
13/157433
Inventors:
Brian J. Campbell - Cupertino CA, US
Daniel C. Murray - Morgan Hill CA, US
Conrad H. Ziesler - Seattle WA, US
Assignee:
Apple Inc. - Cupertino CA
International Classification:
G11C 5/14
US Classification:
365227, 365201, 365226
Abstract:
A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.
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Conrad H Ziesler from Seattle, WA, age ~47 Get Report