Ciaran P Hanrahan

49870904, Jan 22, 1991

Jul 25, 1989

7/385900

Fu-Chieh Hsu - Saratoga CA
Ciaran P. Hanrahan - Fremont CA

Integrated Device Technology, Inc. - Santa Clara CA

H01L 2170

437 52

Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.

52234436, Jun 29, 1993

Feb 19, 1992

7/838539

Jeffrey D. Chinn - Foster City CA
Ciaran P. Hanrahan - Fremont CA

Integrated Device Technology, Inc. - Santa Clara CA

H01L 21302

437 8

An embodiment of the present invention is a method for determining the cleanliness of a semiconductor wafer initially deposited with polysilicon, patterned with photoresist, processed, and then having the resist removed under standard conditions. The method comprising the steps of: depositing a thin TEOS film over the entire surface of a wafer; exposing said wafer to a solution of hot potassium hydroxide (KOH) that attacks polysilicon and is highly selective to and does not etch said TEOS film, the exposing such that if any pin hole exists in the TEOS film an underlying layer of polysilicon is attacked vigorously; and inspecting said wafer for a visual indication in said polysilicon layer of whether or not said polysilicon layer was attacked by the exposure to said potassium hydroxide (KOH).

55983170, Jan 28, 1997

Feb 7, 1996

8/597785

Ciaran Hanrahan - Fremont CA
Andrew P. Stack - San Jose CA

Integrated Device Technology, Inc. - Santa Clara CA

H01G 4005
H01G 406

361313

A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.

55850162, Dec 17, 1996

Jul 20, 1993

8/094676

Ciaran Hanrahan - Fremont CA
Andrew P. Stack - San Jose CA

Integrated Device Technology, Inc. - Santa Clara CA

B23K 2600
H01G 700

21912169

A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.