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Chunhui H Zhang

from Austin, TX
Age ~50
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Also known as:
Chun Z Zhang, Hui Zhang Chun
Phone and address:
4405 Bat Falcon Dr, Austin, TX 78738
Related to:
Zhen Zhang, 51Yan ZhangLu Zhang, 51Jianming ZhangPeifang Zhang, 49Jun Zhang, 39Peifang Zhang, 48Zhihong Pan, 50
Connected to:
Aimei Zhang, 44Aining Zhang, 30Aiqing Zhang, 50Alexia Y Zhang, 36Amy X Zhang, 57Angelina Zhang, 54Ashley C Zhang, 60Baomin Zhang, 55Beilei Zhang, 45Carl Zhang, 33

Chunhui Zhang Phones & Addresses

  • 4405 Bat Falcon Dr, Austin, TX 78738
  • 2683 Overlook Dr, Hillsboro, OR 97124
  • 12878 NW Kyla Ln, Portland, OR 97229
  • 4624 Verano Pl, Irvine, CA 92602 (949) 509-1579
  • 5624 Verano Pl, Irvine, CA 92602 (949) 509-1579 (949) 633-5910

Work

Position: Professional/Technical

Resumes

Resumes

Chunhui Zhang Photo 1

Vice President Of Rd

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Location:
12878 northwest Kyla Ln, Portland, OR 97229
Industry:
Computer Hardware
Work:
Montage Technology, Inc
Vice President of Rd
Hygon/Amd-Jv Feb 2017 - Sep 2019
Director of Architecture
Intel Corporation Sep 2013 - Jan 2017
Cpu Architect
Portland State University Mar 2014 - Jul 2014
Psu Adjunct Faculty
Intel Corporation Nov 2005 - Sep 2013
Cpu Designer and Micro-Architect
Education:
Uc Irvine 2001 - 2005
Doctorates, Doctor of Philosophy Tsinghua University 1993 - 2001
Master of Science, Masters
Skills:
Processors
Computer Architecture
Soc
Asic
Microarchitecture
Rtl Design
Microprocessors
Systemverilog
Fpga
Vhdl
Integrated Circuit Design
Low Power Design
Pcie
Eda
Vlsi
Cmos
Digital Signal Processors
System on A Chip
Application Specific Integrated Circuits
Modelsim
Chunhui Zhang Photo 2

Chunhui Zhang

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Chunhui Zhang Photo 3

Chunhui Zhang

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Chunhui Zhang Photo 4

Chunhui Zhang

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Publications

Us Patents

Generational Thread Scheduler

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US Patent:
20130160020, Jun 20, 2013
Filed:
Dec 16, 2011
Appl. No.:
13/328365
Inventors:
Edward T. Grochowski - San Jose CA, US
Michael D. Upton - Seattle WA, US
George Z. Chrysos - Portland OR, US
Chunhui C. Zhang - Hillsboro OR, US
Mohammed L. Al-Aqrabawi - Hillsboro OR, US
International Classification:
G06F 9/50
US Classification:
718104
Abstract:
Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.

Efficient Range-Based Memory Writeback To Improve Host To Device Communication For Optimal Power And Performance

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US Patent:
20200233664, Jul 23, 2020
Filed:
Dec 17, 2019
Appl. No.:
16/717258
Inventors:
- Santa Clara CA, US
Chunhui Zhang - Portland OR, US
Qixiong J. Bian - Beaverton OR, US
Bret L. Toll - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/30
G06F 12/128
G06F 12/0804
G06F 9/38
G06F 12/0811
G06F 13/28
G06F 12/0891
G06F 12/0875
G06F 12/0842
Abstract:
Method and apparatus for efficient range-based memory writeback is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.

Technologies For Enforcing Coherence Ordering In Consumer Polling Interactions

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US Patent:
20190102301, Apr 4, 2019
Filed:
Sep 29, 2017
Appl. No.:
15/720379
Inventors:
- Santa Clara CA, US
Chunhui Zhang - Hillsboro OR, US
Ren Wang - Portland OR, US
Ram Huggahalli - Costa Mesa CA, US
International Classification:
G06F 12/0831
G06F 9/30
G06F 9/46
H04L 12/741
H04L 12/933
Abstract:
Technologies for enforcing coherence ordering in consumer polling interactions include a network interface controller (NIC) of a target computing device which is configured to receive a network packet, write the payload of the network packet to a data storage device of the target computing device, and obtain, subsequent to having transmitted a last write request to write the payload to the data storage device, ownership of a flag cache line of a cache of the target computing device. The NIC is additionally configured to receive a snoop request from a processor of the target computing device, identify whether the received snoop request corresponds to a read flag snoop request associated with an active request being processed by the NIC, and hold the received snoop request for delayed return in response to having identified the received snoop request as the read flag snoop request. Other embodiments are described herein.

Technologies For Untrusted Code Execution With Processor Sandbox Support

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US Patent:
20190102537, Apr 4, 2019
Filed:
Sep 29, 2017
Appl. No.:
15/720083
Inventors:
- Santa Clara CA, US
Mingqiu Sun - Beaverton OR, US
Ravi L. Sahita - Portland OR, US
Chunhui Zhang - Hillsboro OR, US
Xiaoning Li - Portland OR, US
International Classification:
G06F 21/53
G06F 21/12
G06F 9/38
G06F 9/45
Abstract:
Technologies for untrusted code execution include a computing device having a processor with sandbox support. The computing device executes code included in a native domain in a non-privileged, native processor mode. The computing device may invoke a sandbox jump processor instruction during execution of the code in the native domain to enter a sandbox domain. The computing device executes code in the sandbox domain in a non-privileged, sandbox processor mode in response to invoking the sandbox jump instruction. While executing in the sandbox processor mode, the processor denies access to memory outside of the sandbox domain and may deny execution of one or more prohibited instructions. From the sandbox domain, the computing device may execute a sandbox exit instruction to exit the sandbox domain and resume execution in the native domain. The computing device may execute processor instructions to configure the sandbox domain. Other embodiments are described and claimed.

Efficient Range-Based Memory Writeback To Improve Host To Device Commmunication For Optimal Power And Performance

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US Patent:
20180285105, Oct 4, 2018
Filed:
Mar 31, 2017
Appl. No.:
15/476302
Inventors:
- Santa Clara CA, US
Chunhui Zhang - Portland OR, US
Qixiong J. Bian - Beaverton OR, US
Bret L. Toll - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
International Classification:
G06F 9/30
G06F 12/0875
G06F 12/0891
G06F 12/084
G06F 12/0842
G06F 13/28
Abstract:
Method and apparatus for efficient range-based memory writeback is described herein. One embodiment of an apparatus includes a system memory, a plurality of hardware processor cores each of which includes a first cache, a decoder circuitry to decode an instruction having fields for a first memory address and a range indicator, and an execution circuitry to execute the decoded instruction. Together, the first memory address and the range indicator define a contiguous region in the system memory that includes one or more cache lines. An execution of the decoded instruction causes any instances of the one or more cache lines in the first cache to be invalidated. Additionally, any invalidated instances of the one or more cache lines that are dirty are to be stored to system memory.

Generational Thread Scheduler

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US Patent:
20170031729, Feb 2, 2017
Filed:
Oct 11, 2016
Appl. No.:
15/290375
Inventors:
- Santa Clara CA, US
Michael D. Upton - Seattle WA, US
George Z. Chrysos - Portland OR, US
Chunhui Zhang - Hillsboro OR, US
Mohammed L. Al-Aqrabawi - Portland OR, US
International Classification:
G06F 9/52
Abstract:
Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.

Memory Sequencing With Coherent And Non-Coherent Sub-Systems

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US Patent:
20160011977, Jan 14, 2016
Filed:
Jul 9, 2014
Appl. No.:
14/327109
Inventors:
CHUNHUI ZHANG - Hillsboro OR, US
GEORGE Z. CHRYSOS - Portland OR, US
EDWARD T. GROCHOWSKI - San Jose CA, US
RAMACHARAN SUNDARARAMAN - Hillsboro OR, US
CHUNG-LUN CHAN - Hillsboro OR, US
FEDERICO ARDANAZ - Hillsboro OR, US
International Classification:
G06F 12/08
Abstract:
Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.
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Chunhui H Zhang from Austin, TX, age ~50 Get Report