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Christopher W Leitz

from Watertown, MA
Age ~48
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Also known as:
Christopher William Leitz, Christophe W Leitz, Christophe Christopher Leitz, Chris W Leitz, Christopher W Jacobstein
Phone and address:
41 Columbia St, Watertown, MA 02472
Related to:
Victoria P Jacobson
Connected to:
Joy H Leitz, 72Margaret J Leitz, 83Paula D Leitz, 91Rosalyn R Leitz, 93Rosemary K Leitz, 62Suzanne E Leitz, 62Christina L Leitzel, 36Darlene R Leitzel, 80Denise M Leitzel, 66Erik M Leitzel, 33

Christopher Leitz Phones & Addresses

  • 41 Columbia St, Watertown, MA 02472
  • 109 Spring St, Watertown, MA 02472
  • 97 Prospect St #1, Manchester, NH 03104
  • 262 Main St, Manchester, NH 03102 (603) 668-3206
  • 262 Main St #S, Manchester, NH 03102 (603) 668-3206
  • 1 Clocktower Pl, Nashua, NH 03060 (603) 886-0650
  • Salem, NH
  • Boston, MA
  • Bethlehem, PA

Industries

Semiconductors

Resumes

Resumes

Christopher Leitz Photo 1

Christopher Leitz

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Location:
Greater Boston Area
Industry:
Semiconductors

Publications

Us Patents

Formation Of Planar Strained Layers

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US Patent:
6730551, May 4, 2004
Filed:
Aug 2, 2002
Appl. No.:
10/211126
Inventors:
Minjoo L. Lee - Cambridge MA
Christopher W. Leitz - Nashua NH
Eugene A. Fitzgerald - Windham NH
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L 21337
US Classification:
438191
Abstract:
A structure and a method for forming the structure, the method including forming a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0. 25%. A tensilely strained semiconductor layer is formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer or (ii) having an average height less than 10 nm.

Enhancement Of P-Type Metal-Oxide-Semiconductor Field Effect Transistors

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US Patent:
6916727, Jul 12, 2005
Filed:
Jun 21, 2002
Appl. No.:
10/177571
Inventors:
Christopher W. Leitz - Nashua NH, US
Minjoo L. Lee - Cambridge MA, US
Eugene A. Fitzgerald - Windham NH, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L021/20
US Classification:
438478, 257192
Abstract:
A structure includes a tensile strained layer disposed over a substrate, the tensile strained layer having a first thickness. A compressed layer is disposed between the tensile strained layer and the substrate, the compressed layer having a second thickness. The first and second thicknesses are selected to define a first carrier mobility in the tensile strained layer and a second carrier mobility in the compressed layer.

Semiconductor Heterostructures And Related Methods

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US Patent:
7049627, May 23, 2006
Filed:
Aug 22, 2003
Appl. No.:
10/647074
Inventors:
Christopher Vineis - Cambridge MA, US
Vicky Yang - Windham NH, US
Matthew Currie - Windham NH, US
Richard Westhoff - Hudson NH, US
Christopher Leitz - Manchester NH, US
Assignee:
AmberWave Systems Corporation - Salem NH
International Classification:
H01L 29/06
H01L 21/00
US Classification:
257 18, 257 19, 257191, 257616, 438 37, 438 44, 438 87
Abstract:
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Semiconductor Devices Having Strained Dual Channel Layers

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US Patent:
7138310, Nov 21, 2006
Filed:
Jun 6, 2003
Appl. No.:
10/456926
Inventors:
Matthew T. Currie - Windham NH, US
Anthony J. Lochtefeld - Somerville MA, US
Christopher W. Leitz - Nashua NH, US
Eugene A. Fitzgerald - Windham NH, US
Assignee:
AmberWave Systems Corporation - Salem NH
International Classification:
H01L 21/8238
US Classification:
438199, 438938
Abstract:
A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.

Structures With Planar Strained Layers

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US Patent:
7141820, Nov 28, 2006
Filed:
Feb 27, 2004
Appl. No.:
10/788741
Inventors:
Minjoo L. Lee - Cambridge MA, US
Christopher W. Leitz - Manchester NH, US
Eugene A. Fitzgerald - Windham NH, US
Assignee:
AmberWave Systems Corporation - Salem NH
International Classification:
H01L 29/04
US Classification:
257 65, 257192
Abstract:
A structure including a compressively strained semiconductor layer, the compressively strained layer having a strain greater than or equal to 0. 25%. A tensilely strained semiconductor layer may be formed over the compressively strained layer. The compressively strained layer is substantially planar, having a surface roughness characterized in (i) having an average wavelength greater than an average wavelength of a carrier in the compressively strained layer and/or (ii) having an average height less than 10 nm.

Structure And Method For A High-Speed Semiconductor Device Having A Ge Channel Layer

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US Patent:
7301180, Nov 27, 2007
Filed:
Jun 18, 2002
Appl. No.:
10/173986
Inventors:
Minjoo L. Lee - Cambridge MA, US
Christopher W. Leitz - Nashua NH, US
Eugene A. Fitzgerald - Windham NH, US
Assignee:
Massachusetts Institute of Technology - Cambridge MA
International Classification:
H01L 31/0328
US Classification:
257191, 257192
Abstract:
The invention provides semiconductor structure comprising a strained Ge channel layer, and a gate dielectric disposed over the strained Ge channel layer. In one aspect of the invention, a strained Ge channel MOSFET is provided. The strained Ge channel MOSFET includes a relaxed SiGe virtual substrate with a Ge content between 50-95%, and a strained Ge channel formed on the virtual substrate. A gate structure is formed upon the strained Ge channel, whereupon a MOSFET is formed with increased performance over bulk Si. In another embodiment of the invention, a semiconductor structure comprising a relaxed Ge channel layer and a virtual substrate, wherein the relaxed Ge channel layer is disposed above the virtual substrate. In a further aspect of the invention, a relaxed Ge channel MOSFET is provided. The method includes providing a relaxed virtual substrate with a Ge composition of approximately 100% and a relaxed Ge channel formed on the virtual substrate.

Semiconductor Structures With Structural Homogeneity

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US Patent:
7332417, Feb 19, 2008
Filed:
Jan 27, 2004
Appl. No.:
10/765372
Inventors:
Richard Westhoff - Hudson NH, US
Christopher J. Vineis - Cambridge MA, US
Matthew T. Currie - Windham NH, US
Vicky T. Yang - Windham NH, US
Christopher W. Leitz - Manchester NH, US
Assignee:
AmberWave Systems Corporation - Salem NH
International Classification:
H01L 21/20
H01L 21/36
H01L 21/30
US Classification:
438509, 438455, 257E21097
Abstract:
Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free.

Methods Of Fabricating Semiconductor Heterostructures

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US Patent:
7368308, May 6, 2008
Filed:
Sep 15, 2005
Appl. No.:
11/227770
Inventors:
Christopher Vineis - Watertown MA, US
Vicky Yang - Brookline MA, US
Matthew Currie - Brookline MA, US
Richard Westhoff - Hudson NH, US
Christopher Leitz - Nashua NH, US
Assignee:
AmberWave Systems Corporation - Salem NH
International Classification:
H01L 21/00
H01L 29/06
US Classification:
438 37, 438 87, 257 18, 257 19, 257191
Abstract:
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.
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Christopher W Leitz from Watertown, MA, age ~48 Get Report