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Christian Klingner Phones & Addresses

  • 864 Elmira Dr, Sunnyvale, CA 94087
  • 1967 Paolo Ct, San Jose, CA 95131 (408) 272-8631
  • Santa Clara, CA
  • Santa Cruz, CA

Work

Company: Nvidia Feb 2009 Address: US Headquarters Position: Sr. hardware engineer

Education

Degree: Dimplom School / High School: Technische Universität Dresden 1991 to 1997 Specialities: EE

Skills

Signal Integrity • Spice • Asic • Soc • Rtl Design • Verilog • Processors • Semiconductors • Computer Architecture • Microprocessors • Low Power Design • Ic • Logic Design • Physical Design • Vlsi • Debugging • Embedded Systems • Digital Signal Processors • Perl • Timing • Static Timing Analysis • Circuit Design • Eda • Hardware • Arm • Timing Closure • Logic Synthesis • Hardware Architecture • Tcl • Integrated Circuit Design • Cmos • Pcb Design • Engineering • High Performance Computing • Semiconductor Industry • Cadence Virtuoso • Cadence • Electrical Engineering • Programming • Scripting • Primetime • Unix • Shell Scripting • Place and Route • Formal Verification • Simulations • Linux • Electronics • C

Languages

German • English • Japanese • Russian

Interests

Backpacking • Snowboarding • Scuba • Education • Photography • Windsurfing • Mountain Biking • Snowcamping • Wakeboarding

Industries

Semiconductors

Resumes

Resumes

Christian Klingner Photo 1

Physical Design Methodology Lead

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Location:
300 Pettigru St, Greenville, SC 29601
Industry:
Semiconductors
Work:
NVIDIA - US Headquarters since Feb 2009
Sr. Hardware Engineer

Stream Processors Mar 2007 - Feb 2009
Sr. VLSI Engineer

Transmeta Feb 2000 - Feb 2007
Principal Engineer

Toshiba America Electronic Components Aug 1997 - Sep 1999
Logic Design Engineer

Toshiba (Japan) Sep 1995 - Mar 1997
Internship
Education:
Technische Universität Dresden 1991 - 1997
Dimplom, EE
Skills:
Signal Integrity
Spice
Asic
Soc
Rtl Design
Verilog
Processors
Semiconductors
Computer Architecture
Microprocessors
Low Power Design
Ic
Logic Design
Physical Design
Vlsi
Debugging
Embedded Systems
Digital Signal Processors
Perl
Timing
Static Timing Analysis
Circuit Design
Eda
Hardware
Arm
Timing Closure
Logic Synthesis
Hardware Architecture
Tcl
Integrated Circuit Design
Cmos
Pcb Design
Engineering
High Performance Computing
Semiconductor Industry
Cadence Virtuoso
Cadence
Electrical Engineering
Programming
Scripting
Primetime
Unix
Shell Scripting
Place and Route
Formal Verification
Simulations
Linux
Electronics
C
Interests:
Backpacking
Snowboarding
Scuba
Education
Photography
Windsurfing
Mountain Biking
Snowcamping
Wakeboarding
Languages:
German
English
Japanese
Russian

Publications

Us Patents

Repeater Circuit Having Different Operating And Reset Voltage Ranges, And Methods Thereof

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US Patent:
7595664, Sep 29, 2009
Filed:
Feb 6, 2007
Appl. No.:
11/703323
Inventors:
Robert Paul Masleid - Monte Sereno CA, US
Vatsal Dholabhai - Portola Valley CA, US
Christian Klingner - San Jose CA, US
International Classification:
H03K 19/0175
H03K 19/094
US Classification:
326 86, 326 23, 326 27
Abstract:
A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Repeater Circuit Having Different Operating And Reset Voltage Ranges, And Methods Thereof

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US Patent:
20050270069, Dec 8, 2005
Filed:
Jun 28, 2004
Appl. No.:
10/879808
Inventors:
Robert Masleid - Monte Sereno CA, US
Vatsal Dholabhai - Portola Valley CA, US
Christian Klingner - San Jose CA, US
International Classification:
H03K019/094
US Classification:
326121000
Abstract:
A circuit for assisting signal transitions on a wire, and a method thereof. A first subcircuit causes a first transistor that is coupled to the circuit's output to turn on during a rising transition and drive the output to a high state to assist in the rising transition. A second subcircuit causes a second transistor that is coupled to the circuit's output to turn on during a falling transition and drive the output to a low state to assist in the falling transition. A third subcircuit resets elements of the first subcircuit. The first subcircuit operates above a first voltage threshold and the third subcircuit operates below the first voltage threshold. A fourth subcircuit resets elements of the second subcircuit. The second subcircuit operates below a second voltage threshold and the fourth subcircuit operates above the second voltage threshold.

Fast-Bypass Memory Circuit

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US Patent:
20130155781, Jun 20, 2013
Filed:
Dec 15, 2011
Appl. No.:
13/327693
Inventors:
Venkata Kottapalli - Fremont CA, US
Scott Pitkethly - San Francisco CA, US
Christian Klingner - Sunnyvale CA, US
Matthew Gerlach - Plymouth MI, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G11C 7/10
US Classification:
36518905
Abstract:
A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.

Fast-Bypass Memory Circuit

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US Patent:
20130155783, Jun 20, 2013
Filed:
Apr 13, 2012
Appl. No.:
13/447037
Inventors:
Venkata Kottapalli - Fremont CA, US
Scott Pitkethly - San Francisco CA, US
Christian Klingner - Sunnyvale CA, US
Matthew Gerlach - Plymouth MI, US
Assignee:
NVIDIA CORPORATION - Santa Clara CA
International Classification:
G11C 7/10
US Classification:
36518905
Abstract:
A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection logic. The upstream memory logic is configured to latch the input data on receiving the clock pulse. The downstream memory logic is configured to store the latched input data. The selection logic is configured to expose a logic level dependent on whether the upstream memory logic has latched the input data, the exposed logic level derived from the input data before the input data is latched, and from the latched input data after the input data is latched.
Christian Klingner from Sunnyvale, CA, age ~52 Get Report