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Chris Nauert Phones & Addresses

  • Dripping Springs, TX
  • Mansfield, TX
  • 131 Briar Forest Dr, Bastrop, TX 78602 (512) 303-3016
  • 931 Briar Forest Dr, Bastrop, TX 78602 (512) 303-3016
  • 11408 Naples Cv, Austin, TX 78739 (512) 689-6400
  • 3006 Wadsworth Way, Austin, TX 78748
  • 9024 Northgate Blvd, Austin, TX 78758 (512) 836-6851

Business Records

Name / Title
Company / Classification
Phones & Addresses
Chris Nauert
Manager
GROUP VENTURE PROPERTIES, LLC
Nonresidential Building Operator
12513 Rush Crk Ln, Austin, TX 78732
7609 Lantern Vw Dr, Leander, TX 78645
17704 Regatta Vw Dr, Leander, TX 78645
2707 Brubeck Bnd, Cedar Park, TX 78613

Publications

Us Patents

Processes For Forming Electronic Devices Including Polishing Metal-Containing Layers

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US Patent:
7915169, Mar 29, 2011
Filed:
Nov 2, 2007
Appl. No.:
11/934628
Inventors:
Christopher E. Brannon - Pflugerville TX, US
Michael Wedlake - Austin TX, US
Chris A. Nauert - Austin TX, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/302
US Classification:
438691, 438690
Abstract:
A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Processes For Forming Electronic Devices Including Polishing Metal-Containing Layers

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US Patent:
8232209, Jul 31, 2012
Filed:
Feb 11, 2011
Appl. No.:
13/025979
Inventors:
Christopher E. Brannon - Pflugerville TX, US
Michael Wedlake - Austin TX, US
Chris A. Nauert - Austin TX, US
Assignee:
Spansion LLC - Sunnyvale CA
International Classification:
H01L 21/302
US Classification:
438692
Abstract:
A process of forming an electronic device can include providing a workpiece. The workpiece can include a substrate, an interlevel dielectric overlying the substrate, a refractory-metal-containing layer over the interlevel dielectric, and a first metal-containing layer over the refractory-metal-containing layer. The first metal-containing layer can include a metal element other than a refractory metal element. The process further includes polishing the first metal-containing layer and the refractory-metal-containing layer as a continuous action to expose the interlevel dielectric. In one embodiment, the metal element can include copper, nickel, or a noble metal. In another embodiment, polishing can be performed using a selectivity agent to reduce the amount of the interlevel dielectric removed.

Method To Achieve A Low Cost Transistor Isolation Dielectric Process Module With Improved Process Control, Process Cost, And Yield Potential

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US Patent:
20080157289, Jul 3, 2008
Filed:
Dec 27, 2006
Appl. No.:
11/616384
Inventors:
Chris A. Nauert - Austin TX, US
Assignee:
SPANSION LLC - Sunnyvale CA
International Classification:
H01L 21/302
H01L 23/58
US Classification:
257635, 438693, 257E21214, 257E23002
Abstract:
A method of processing a semiconductor structure is provided. The method includes forming a polish stop layer over one or more features on a substrate; forming a first dielectric layer over the polish stop layer, a valley portion of the first dielectric layer being just above a top of the polish stop layer; and polishing the dielectric layer down to the top of the polish stop layer. By forming a just enough dielectric layer to allow gap-fill on the substrate and polishing the dielectric layer down to the top of the polish stop layer, the method can reduce the cost and controls associated with forming the first dielectric layer.

Methodology For Improved Semiconductor Process Monitoring Using Optical Emission Spectroscopy

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US Patent:
60467967, Apr 4, 2000
Filed:
Apr 22, 1998
Appl. No.:
9/064470
Inventors:
Richard J. Markle - Austin TX
Michael J. Gatto - Austin TX
Chris A. Nauert - Austin TX
Yi Cheng - Dallas TX
Richard B. Patty - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
G01N 2162
G01N 3100
US Classification:
356 72
Abstract:
In a semiconductor process which utilizes a plasma within a process tool chamber, a method of using optical emission spectroscopy (OES) to monitor a particular parameter of the process is disclosed. A first wavelength present in the plasma is determined which varies highly in intensity depending on the particular parameter by observing a statistically significant sample representing variations of the particular parameter. A second wavelength of chemical significance to the process is also determined which is relatively stable in intensity over time irrespective of variations of the particular parameter, also by observing a statistically significant sample representing variations of the particular parameter. These two wavelengths may be determined from test wafers and off-line physical measurements. Then, the intensity of the first and second wavelengths present in the plasma is measured on-line during normal processing within the process tool chamber, and the ratio between the first and second wavelength's respective intensities generates a numeric value which is correlated to the particular parameter.
Chris Alan Nauert from Dripping Springs, TX, age ~51 Get Report