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Mou Ching Lin

from High Bridge, NJ
Age ~75
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Also known as:
Mou C Lin, Ching Mou Lin, Ching Lin Mou, Lin C Mou
Phone and address:
10 Highview Dr, High Bridge, NJ 08829
Connected to:
Aaron E Lin, 62Ai Lin, 69Angela X Lin, 51Antoine W Lin, 46Bennie Lin, 52Bevin Lin, 45Bi Q Lin, 47Bill T Lin, 69Blaise C Lin, 69Botao Lin, 40

Mou Lin Phones & Addresses

  • 10 Highview Dr, High Bridge, NJ 08829
  • Califon, NJ
  • Lebanon, NJ
  • Hialeah, FL

Publications

Us Patents

Bank-Based Input/Output Buffers With Multiple Reference Voltages

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US Patent:
6859066, Feb 22, 2005
Filed:
Feb 28, 2003
Appl. No.:
10/377320
Inventors:
Arifur Rahman - Yonkers NY, US
William Andrews - Emmaus PA, US
Mou C. Lin - High Bridge NJ, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K019/094
US Classification:
326 63, 326 41
Abstract:
A bank of input/output buffers are configured such that each input buffer in the bank may select from a plurality of voltage references during single-ended operation. Similarly, the pad associated with each input buffer may serve to supply one of the voltage references for other input buffers within the bank.

Programmable Signal Termination For Fpgas And The Like

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US Patent:
6924659, Aug 2, 2005
Filed:
Jul 28, 2003
Appl. No.:
10/628657
Inventors:
William B. Andrews - Emmaus PA, US
Mou C. Lin - High Bridge NJ, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K017/16
US Classification:
326 30, 326 83, 326 86, 326 90, 327108
Abstract:
A termination scheme for the I/O circuitry of a programmable device, such as a field-programmable gate array (FPGA), has programmable resistors switchably connected between reference voltages and two of the device's I/O pads and additional programmable resistors switchably connected between the two I/O pads. By appropriately controlling the reference voltages and the resistance levels, a single implementation of the termination scheme can be used to conform to a relatively wide variety of symmetric and non-symmetric complementary and differential signaling applications.

Programmable I/O Structure For Fpgas And The Like Having Shared Circuitry

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US Patent:
6943582, Sep 13, 2005
Filed:
Sep 25, 2003
Appl. No.:
10/671363
Inventors:
William B. Andrews - Emmaus PA, US
Mou C. Lin - High Bridge NJ, US
John Schadt - Bethlehem PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K019/177
US Classification:
326 41, 326 47
Abstract:
A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i. e. , when the outgoing signal is not to be presented at that pad).

Programmable I/O Structure For Fpgas And The Like Having Reduced Pad Capacitance

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US Patent:
6943583, Sep 13, 2005
Filed:
Sep 25, 2003
Appl. No.:
10/671378
Inventors:
William B. Andrews - Emmaus PA, US
Mou C. Lin - High Bridge NJ, US
Harold Scholz - Allentown PA, US
Arifur Rahman - Yonkers NY, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K019/177
US Classification:
326 41, 326 47
Abstract:
A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i. e. , when the outgoing signal is not to be presented at that pad).

Electronic Circuit With On-Chip Programmable Terminations

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US Patent:
6967500, Nov 22, 2005
Filed:
Mar 26, 2003
Appl. No.:
10/397669
Inventors:
Mou C. Lin - High Bridge NJ, US
William Andrews - Emmaus PA, US
Arifur Rahman - Yonkers NY, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K017/16
US Classification:
326 30, 326 38, 326 44
Abstract:
An electronic circuit with programmable terminations includes a circuit block, signal pads coupled to the circuit block, programmable termination circuits each associated with a corresponding one of the signal pads, and a reference circuit operative to generate one or more control signals for application to the programmable termination circuits. A given one of the programmable termination circuits is configurable independently of at least one of the other programmable termination circuits into one of a plurality of termination states. Preferably, the programmable termination circuits are each independently configurable to provide a particular termination resistance and a particular supply terminal connection type for the associated signal pad. The invention is particularly well suited for use in integrated circuit applications, such as, for example, those involving FPGAs, FPSCs and ASICs.

Programmable Logic Device Having A Configurable Dram With Transparent Refresh

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US Patent:
7129749, Oct 31, 2006
Filed:
Oct 27, 2004
Appl. No.:
10/974305
Inventors:
Larry R. Fenstermaker - Nazareth PA, US
John A. Schadt - Bethlehem PA, US
Mou C. Lin - High Bridge NJ, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/177
US Classification:
326 41, 326 82
Abstract:
A programmable logic device (PLD) having a programmable routing structure that employs non-static memory cells, such as dynamic random access memory (DRAM) cells, to control configurable circuit elements, such as pass-transistors and/or MUXes. In a representative embodiment, each DRAM cell is connected to its corresponding configurable circuit element using a buffer adapted to stabilize the output voltage generated by the cell and offset the effect of charge leakage from the cell capacitor. In addition, refresh circuitry associated with the DRAM cell periodically restores the charge in the cell capacitor using a refresh operation that is performed in the background, without disturbing the user functions of the PLD. Advantageously, a relatively large capacitance associated with a DRAM cell makes a PLD of the invention less susceptible to soft errors than a prior-art PLD that relies on SRAM cells for configuration control of its routing structure.

Low Power Asynchronous Sense Amp

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US Patent:
7161862, Jan 9, 2007
Filed:
Nov 22, 2004
Appl. No.:
10/996283
Inventors:
Mou C. Lin - High Bridge NJ, US
Zheng Chen - Macungie PA, US
Larry R. Fenstermaker - Nazareth PA, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
G11C 7/02
US Classification:
365207, 365205
Abstract:
A memory sense amplifier includes an output and a complement output. The sense amplifier is configured such that a memory cell driving the bit line low enables latching of the bit line low by enabling pull-up of the complement output, and the memory cell driving the complement bit line low enables latching of the complement bit line low by enabling pull-up of the output.

Interface Circuitry For Electrical Systems

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US Patent:
7215149, May 8, 2007
Filed:
Dec 15, 2004
Appl. No.:
11/012550
Inventors:
William B. Andrews - Emmaus PA, US
Larry R. Fenstermaker - Nazareth PA, US
John Schadt - Bethlehem PA, US
Mou C. Lin - High Bridge NJ, US
Assignee:
Lattice Semiconductor Corporation - Hillsboro OR
International Classification:
H03K 19/0175
US Classification:
326 83, 326 81
Abstract:
An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.
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Mou Ching Lin from High Bridge, NJ, age ~75 Get Report