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Oliver C Kao

from Cupertino, CA
Age ~63
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Also known as:
Oliver Chihkuang Kao, Chih Kuang Kao, Chih Chien Kao, Chih C Kao, Chih K Kao, Kao C Oliver, Chi H Kao, Chihkuang Kao Oliver
Related to:
Che Lin Kao, 47Roger Kao, 72Deager Kao, 41Yun C Kao, 45Li Kao, 72
Connected to:
Alexander C Kao, 58Benjamin J Kao, 47Beth T Kao, 44Chia P Kao, 47Chih P Kao, 45Collin Kao, 46Crystal J Kao, 28Dan M Kao, 67Diane Kao, 34Flora T Kao, 46

Oliver Kao Phones & Addresses

  • Cupertino, CA
  • Sunnyvale, CA
  • San Jose, CA
  • Santa Clara, CA

Resumes

Resumes

Oliver Kao Photo 1

Senior Hardware Design Engineer

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Location:
1855 Beaver Ridge Cir, Norcross, GA 30071
Industry:
Electrical/Electronic Manufacturing
Work:
St. Jude Medical - Sunnyvale since 2012
Sr Hardware Design Engineer
Texas Instruments - Tucson, Arizona Area 2011 - 2012
Digital Design Engineer
Design Contractor 2009 - 2010
Design Contractor
Atmel 2001 - 2008
Design Manager
ISD/Winbond 1998 - 2001
Senior Design Engineer
Education:
University of Florida 1983 - 1986
MS in EE, Physics, Solid-State Microelectronics National Cheng Kung University 1979 - 1983
BS, Physics
Skills:
Verilog
Rtl Design
Semiconductors
Microprocessors
Ic
Atpg
Oliver Kao Photo 2

Design Manager At Atmel

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Location:
1600 Technology Dr, San Jose, CA 95110
Industry:
Computer Hardware
Work:
Atmel Corporation
Design Manager at Atmel

Publications

Us Patents

Test Circuit For Input-To-Output Speed Measurement

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US Patent:
6768333, Jul 27, 2004
Filed:
May 13, 2003
Appl. No.:
10/437862
Inventors:
Oliver C. Kao - Cupertino CA
Gladwyn O. DSouza - Los Gatos CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G01R 3126
US Classification:
324765, 3241581, 324161
Abstract:
A test circuit aids in accurately measuring the input pin to output pin signal propagation speed through an integrated circuit by providing a D flip-flop in the signal path near the output pad to register the arrival of a test signal transition. The flip-flop is clocked at various clock frequencies. At the high frequencies, test signal transitions applied at the input pad coincident with a clock transition having not arrived at the output pad in time to be registered at the next clock transition. At lower clock frequencies, the test transition has time to propagate through the integrated circuit and thus will be registered by the flip-flop. By successively lowering the clock frequency and sending test signals through the circuit, one-half of that clock period that just registers the test signal transition corresponds to the input-to-output delay time being measured.

Multiple Message Multilevel Analog Signal Recording And Playback System Having Memory Array Configurable For Analog And Digital Storage And Serial Communication

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US Patent:
6865186, Mar 8, 2005
Filed:
Feb 10, 2000
Appl. No.:
09/501699
Inventors:
Geoffrey B. Jackson - Campbell CA, US
Saleel V. Awsare - Redwood City CA, US
Ming-Bing Chang - Santa Clara CA, US
Peter Holzmann - Campbell CA, US
Oliver Chihkuang Kao - Cupertino CA, US
Hung-Chuan Pai - San Jose CA, US
Carl R. Palmer - Los Gatos CA, US
Aditya Raina - San Jose CA, US
Assignee:
Windbond Electronics Corporation - Hsinchu
International Classification:
H04L012/28
US Classification:
370419, 370535, 370537
Abstract:
A multilevel analog recording and playback system is described. An analog processing circuit processes analog data. A storage circuit includes a non-volatile memory array, a switching circuit, and a communication interface. The non-volatile memory array stores analog and digital data. The switching circuit transfers the analog and digital data to and from the memory array. The communication interface allows a processor to exchange information with the device.

Programmable Logic Auto Write-Back

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US Patent:
7183801, Feb 27, 2007
Filed:
Sep 8, 2004
Appl. No.:
10/937817
Inventors:
Oliver C. Kao - Cupertino CA, US
Nancy D. Kunnari - Los Altos CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H03K 19/177
US Classification:
326 40, 326 41
Abstract:
A first configuration controller loads configuration data into a programmable logic device. The first controller is coupled with a first configuration memory and manages couplings of the memory to a first load path. The load path couples to a latch ring, which receives configuration data from the first memory. An array of configuration latches receives the configuration from the latch ring and effects a configuration of the programmable device. A write-back path couples the latch ring and first configuration memory. A write-back controller manages write-back operations of configuration data from the latch ring to the configuration memory. A second configuration controller is coupled to a second configuration memory, which is coupled to a second load path. The second controller and second memory operate like the first. The write-back controller can be configured to couple to the second memory and facilitate development processes by a writing-back developmental configurations.

Multiple Message Multilevel Analog Signal Recording And Playback System Containing Configurable Analog Processing Functions

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US Patent:
7197299, Mar 27, 2007
Filed:
Jan 7, 2004
Appl. No.:
10/752630
Inventors:
Geoffrey B. Jackson - Campbell CA, US
Saleel V. Awsare - Redwood City CA, US
Lawrence D. Engh - Redwood City CA, US
Peter Holzmann - Campbell CA, US
Oliver C. Kao - Cupertino CA, US
Carl R. Palmer - Los Gatos CA, US
Aditya Raina - Santa Clara CA, US
Assignee:
Winbond Electronics Corporation - Hsinchu
International Classification:
H04Q 7/22
H04B 1/28
US Classification:
4554121, 455333, 4555759
Abstract:
A multilevel analog recording and playback system is described. The analog recording and playback system provides a variety of analog processing functions to enhance system level integration. The analog recording and playback system is an fully configurable integrated device that includes a plurality of signal paths, a microphone automatic gain control (“AGC”) circuit, volume control and filtering circuit, speaker driver circuit, gain selectable analog input, auxiliary input and output paths, configurable summation amplifiers having mixing features, multilevel analog memory storage array, and user selectable programming duration.

Apparatus And Method For Reducing Power Consumption In Electronic Devices

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US Patent:
7437584, Oct 14, 2008
Filed:
Feb 27, 2006
Appl. No.:
11/362654
Inventors:
Oliver C. Kao - Cupertino CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G06F 1/32
US Classification:
713322, 326 39, 326 41, 713601
Abstract:
An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being used by the corresponding macrocell, thereby preventing unnecessary toggling and power consumption.

Apparatus And Method For Implementing An Analog-To-Digital Converter In Programmable Logic Devices

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US Patent:
7446690, Nov 4, 2008
Filed:
Nov 6, 2006
Appl. No.:
11/556982
Inventors:
Oliver C. Kao - Cupertino CA, US
Assignee:
Atmel Corporation - San Jose CA
International Classification:
H03M 1/12
US Classification:
341155, 341139, 341141, 341142, 341159
Abstract:
An apparatus and method for providing an analog-to-digital converter (ADC) in programmable logic devices is disclosed. A plurality of multi-purpose input/output (I/O) blocks is configured to provide analog-to-digital conversion and other I/O functionality. The plurality of multi-purpose I/O blocks is also configured to save power when ADC mode is disabled.

Low Power Implementation For Input Signals Of Integrated Circuits

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US Patent:
6765433, Jul 20, 2004
Filed:
Mar 20, 2003
Appl. No.:
10/393583
Inventors:
Oliver C. Kao - Cupertino CA
Assignee:
Atmel Corporation - San Jose CA
International Classification:
G05F 110
US Classification:
327544, 327185, 713326, 365227
Abstract:
Integrated circuit device that uses tristate switching means to disconnect input/output pins from input buffers during a power down mode, thereby preventing current leakage through partially turned on MOS transistors inside input buffers. A transition detection means connected between the input/output pins and the controlling inputs of the tristate switching means monitors electronic signal at the input/output pins while the chip is in a power-down mode and turns on the tristate switching means when a signal transition is detected.
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Oliver C Kao from Cupertino, CA, age ~63 Get Report