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Seng C Lim

from San Jose, CA
Age ~51
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Also known as:
Seng Chen Lim, Chen Lim Seng, Lim Seng Chen, Chen Lim, Seng Chen, Chen Lim N, N Chen Lim, N Lim
Related to:
Kahsing LimCassie Chang, 62Cheng T Chang, 68Jennifer D Chang, 33Jennifer ChengChengtze ChangSing LimChristine D Chang, 32
Connected to:
Adam R Lim, 48Adelaida G Lim, 80Adelfa B Lim, 68Aleksey Lim, 68Alex Lim, 50Alexandra M Lim, 44Alika Lim, 38Alison C Lim, 41Althea Lim, 44Alysia Lim, 35

Seng Lim Phones & Addresses

  • San Jose, CA
    • s
  • DPO, AE
  • Logan, UT
  • 6386 Bollinger Rd, San Jose, CA 95129

Work

Position: Food Preparation and Serving Related Occupations

Business Records

Name / Title
Company / Classification
Phones & Addresses
Seng W. Lim
President
EKC TECHNOLOGY, INC
Mfg Chemical Preparations · Polish and Other Sanitation Good Manufacturing
2520 Barrington Ct, Hayward, CA 94545
PO Box 3703, Hayward, CA 94540
(510) 784-9105
Seng Hee Lim
Lim & Te Investments, LLC
Machine Shop
270 Kinney Dr, San Jose, CA 95112

Publications

Us Patents

Mechanically Interlocking Ball Grid Array Packages And Method Of Making

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US Patent:
6512293, Jan 28, 2003
Filed:
Jun 5, 2001
Appl. No.:
09/875055
Inventors:
Chok J. Chia - Cupertino CA
Seng Sooi Lim - San Jose CA
Wee K. Liew - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2304
US Classification:
257730, 257737, 438666
Abstract:
A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.

Overmold Integrated Circuit Package

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US Patent:
6519844, Feb 18, 2003
Filed:
Aug 27, 2001
Appl. No.:
09/940130
Inventors:
Kumar Nagarajan - San Jose CA
Seng Sooi Lim - San Jose CA
Chok J. Chia - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H05K 330
US Classification:
29841, 29840, 257711, 257778, 257780, 257789, 438108, 438126, 438127
Abstract:
An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound.

Molded Integrated Circuit Package

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US Patent:
6525421, Feb 25, 2003
Filed:
May 1, 2001
Appl. No.:
09/846080
Inventors:
Chok J. Chia - Cupertino CA
Seng S. Lim - San Jose CA
Wee K. Liew - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2304
US Classification:
257730, 257706, 257707, 257778, 438108, 438122, 438125
Abstract:
A mold for use in encapsulating an integrated circuit, wherein an encapsulant is injected into the mold during packaging of the integrated circuit. The improvement to the mold is a shaped member having an abutting surface for contacting a surface of the integrated circuit and thereby substantially preventing encapsulant from adhering to the surface of the integrated circuit, whereby the surface of the integrated circuit is left exposed. Because the surface of the integrated circuit is left exposed, the encapsulant used to encapsulate the integrated circuit does not form a thermal barrier between the integrated circuit and the exterior of the package. Thus, the packaged integrated circuit is able to more efficiently conduct heat away from the integrated circuit.

Semiconductor Package With Wire Bond Arrangement To Reduce Cross Talk For High Speed Circuits

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US Patent:
20060065983, Mar 30, 2006
Filed:
Sep 30, 2004
Appl. No.:
10/956656
Inventors:
Chok Chia - Cupertino CA, US
Wee Liew - San Jose CA, US
Seng Lim - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 23/52
US Classification:
257782000
Abstract:
A package for reducing signal cross talk between wire bonds of semiconductor packages. The package includes a semiconductor die having a plurality of bond pads formed thereon. The bond pads arranged in a first subset of bond pads and a second subset of bond pads. The package also includes a substrate having a plurality of contact points, the plurality of contact points are arranged in a first subset of contact points and a second subset of contact points. To reduce signal cross talk, the wire bonds are arranged such that a first subset of wire bonds are electrically coupled between the first subset of bond pads and the first subset of the contact points. The first subset of wire bonds have ball bonds formed on the first subset of bond pads and stitch bonds formed on the first subset of contact points respectively. A second subset of wire bonds are electrically coupled between the second subset of bond pads and the second subset of the contact points. The second subset of wire bonds have stitch bonds formed on the first subset of bond pads and ball bonds formed on the first subset of contact points respectively. The different height profiles of the first set and the second set of wire bonds tends to reduce signal cross talk between the wires.

Process For Using A Removeable Plating Bus Layer For High Density Substrates

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US Patent:
59813113, Nov 9, 1999
Filed:
Jun 25, 1998
Appl. No.:
9/104838
Inventors:
Chok J. Chia - Cupertino CA
Seng Sooi Lim - San Jose CA
Patrick Variot - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2158
H01L 2148
H01L 2128
H01L 21304
US Classification:
438106
Abstract:
A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating. Electroplating the exposed trace areas on the IC substrate with conductive material (such as gold or nickel) by using the removable plating bus as the electrical connection to the exposed metal traces and removing the removable plating bus after electroplating is finished.

System And Method For Packaging An Integrated Circuit Using Encapsulant Injection

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US Patent:
60819979, Jul 4, 2000
Filed:
Aug 14, 1997
Appl. No.:
8/911418
Inventors:
Chok J. Chia - Cupertino CA
Seng Sooi Lim - San Jose CA
Maniam Alagaratnam - Cupertino CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H05K 330
US Classification:
29841
Abstract:
A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i. e. , a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant. The liquid encapsulant is preferably a C4 underfill material.
Control profile
Seng C Lim from San Jose, CA, age ~51 Get Report