Chanro Park

6849465, Feb 1, 2005

Jun 20, 2003

10/600920

Chanro Park - Fishkill NY, US
Gill Yong Lee - Wappingers Falls NY, US

Infineon Technologies AG - Munich

H01L 2100

438 3, 438171, 438210, 257295, 365145, 365171

A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

8421165, Apr 16, 2013

May 11, 2010

12/777877

Wei-Yip Loh - Austin TX, US
Kanghoon Jeon - Albany CA, US
Chanro Park - Austin TX, US

Sematech, Inc. - Austin TX

H01L 21/02
H01L 21/336

257410, 257288, 438286

Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e. g. , electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction.

8432020, Apr 30, 2013

Jun 4, 2010

12/794251

Chanro Park - Austin TX, US
Sangduk Park - Hwaseong-si, KR
Paul D. Kirsch - Austin TX, US
David Gilmer - Austin TX, US
Chang Yong Kang - Austin TX, US
Joel Barnett - Austin TX, US

Sematech, Inc. - Austin TX

H01L 29/92
H01L 21/02

257532, 257E29343, 257E21008, 438393

Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

20100032642, Feb 11, 2010

Aug 6, 2008

12/187258

Chanro Park - Austin TX, US
Rainer Leuschner - Regensburg, DE

H01L 21/283
H01L 45/00

257 4, 438652, 257E21159, 257E45002

According to an embodiment, a method of manufacturing an integrated circuit including a plurality of resistivity changing memory cells is provided. The method includes: forming a stack of layers including a resistivity changing layer, a first conductive layer, a second conductive layer, and a patterned masking layer which are stacked above each other in this order; patterning the second conductive layer using the masking layer as a patterning mask; patterning the first conductive layer using the second conductive layer as a patterning mask; and patterning the resistivity changing layer using the first conductive layer as a patterning mask.

20110278657, Nov 17, 2011

May 11, 2010

12/777866

Kwan-Yong Lim - Seongnam-Si, KR
Chanro Park - Austin TX, US
Hokyung Park - Latham NY, US
Paul Kirsch - Austin TX, US

H01L 29/788
H01L 21/326
H01L 21/336

257316, 438264, 438466, 257E293, 257E21422, 257E21327

An apparatus, system, and method for a capacitance change non-volatile memory device. The apparatus may include a substrate, a source region in the substrate, a drain region in the substrate, a tunnel oxide layer on the substrate substantially between the source region and the drain region, a floating gate layer on the tunnel oxide layer, a resistance changing material layer on the floating gate layer, and a control gate on the resistance changing material layer.

20130244422, Sep 19, 2013

Mar 16, 2012

13/422439

Xunyuan Zhang - Albany NY, US
Hoon Kim - Guilderland NY, US
Chanro Park - Clifton Park NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 21/768

438653, 257E21584

Disclosed herein are various methods of forming copper-based conductive structures on semiconductor devices, such as transistors. In one example, the method involves performing a first etching process through a patterned metal hard mask layer to define an opening in a layer of insulating material, performing a second etching process through the opening in the layer of insulating material that exposes a portion of an underlying copper-containing structure, performing a wet etching process to remove the patterned metal hard mask layer, performing a selective metal deposition process through the opening in the layer of insulating material to selectively form a metal region on the copper-containing structure and, after forming the metal region, forming a copper-containing structure in the opening above the metal region.

20130299994, Nov 14, 2013

May 8, 2012

13/466895

Chanro Park - Clifton Park NY, US
Errol T. Ryan - Clifton Park NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 23/48
H01L 21/768

257774, 438653, 438675, 257E21584, 257E23011

Integrated circuits and processes for forming integrated circuits are provided. An exemplary process for forming an integrated circuit includes providing a substrate including an oxide layer and a protecting layer disposed over the oxide layer. A recess is etched through the protecting layer and at least partially into the oxide layer. A barrier material is deposited in the recess to form a barrier layer over the oxide layer and protecting layer in the recess. Electrically-conductive material is deposited over the barrier layer in the recess to form the embedded electrical interconnect. The embedded electrical interconnect and barrier layer are recessed to an interconnect recess depth and a barrier recess depth, respectively, within the substrate. At least a portion of the protecting layer remains over the oxide layer after recessing the barrier layer and is removed after recessing the barrier layer.

20140070283, Mar 13, 2014

Sep 10, 2012

13/607954

Hoon Kim - Guilderland NY, US
Kisik Choi - Grand Cayman, KY
Chanro Park - Clifton Park NY, US

GLOBALFOUNDRIES INC. - Grand Cayman

H01L 21/28
H01L 29/78

257288, 438592

An improved field effect transistor and method of fabrication are disclosed. A barrier layer stack is formed in the base and sidewalls of a gate cavity. The barrier layer stack has a first metal layer and a second metal layer. A gate electrode metal is deposited in the cavity. The barrier layer stack is thinned or removed on the sidewalls of the gate cavity, to more precisely control the voltage threshold of the field effect transistor.