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Brian James Cagno

from Tucson, AZ
Age ~49
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Also known as:
Brian J Cagno, Brian Colleen Cagno, Brian D Cagno, Brian J Cango, Brian J Cagn
Phone and address:
8340 E Big Horn Trl, Tucson, AZ 85750
Connected to:
Charles M Cagno, 82Lisa M Cagno, 63Victor A Cagno, 52Angela M Cagnolatti, 46Kimberly D Cagnolatti, 54Edward E Cagnon, 81Ricardo R Cagua, 53Jorge W Caguano, 49Maria J Caguao, 67Jewel E Caguiat, 42

Brian Cagno Phones & Addresses

  • 8340 E Big Horn Trl, Tucson, AZ 85750
  • 8861 Windflower Dr, Tucson, AZ 85715
  • 5363 Sabino Canyon Rd, Tucson, AZ 85750 (520) 529-0504
  • Collegeville, PA
  • Little Egg Harbor Twp, NJ
  • Ellicott City, MD
  • Brookfield, CT
  • 8340 E Big Horn Trl, Tucson, AZ 85750 (520) 906-3614

Work

Company: Reveal technologies Oct 1999 to Oct 2000 Position: Partner and hardware development engineer

Education

Degree: Bachelors, Bachelor of Science School / High School: Bucknell University 1993 to 1997 Specialities: Electronics Engineering, Electronics

Skills

Storage Systems • Storage Enclosures • Fibre Channel • Sas • Sata • Pcie • Cross Functional Team Leadership • Global Cross Functional Team Leadership • Multidisciplinary Design

Emails

b***[email protected]

Industries

Information Technology And Services

Resumes

Resumes

Brian Cagno Photo 1

Engineer

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Location:
Tucson, AZ
Industry:
Information Technology And Services
Work:
Reveal Technologies Oct 1999 - Oct 2000
Partner and Hardware Development Engineer
Ibm Oct 1999 - Oct 2000
Engineer
Synaptyx Telco Systems Jun 1997 - Oct 1999
Hardware Development Engineer
Education:
Bucknell University 1993 - 1997
Bachelors, Bachelor of Science, Electronics Engineering, Electronics
Skills:
Storage Systems
Storage Enclosures
Fibre Channel
Sas
Sata
Pcie
Cross Functional Team Leadership
Global Cross Functional Team Leadership
Multidisciplinary Design

Business Records

Name / Title
Company / Classification
Phones & Addresses
Brian Cagno
Manager
REVEAL TECHNOLOGIES, LLC
5363 N Sabino Cyn Rd #14, Tucson, AZ 85750
PO Box 1679, Ellicott City, MD 21041

Publications

Us Patents

Communication Between Logical Macros

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US Patent:
7103690, Sep 5, 2006
Filed:
Oct 5, 2004
Appl. No.:
10/958967
Inventors:
Gary W. Batchelor - Tucson AZ, US
Brian J. Cagno - Tucson AZ, US
Renee S. LaMar - Tucson AZ, US
Michael L. Harper - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/36
G11C 8/00
US Classification:
710113, 710309, 711203, 370916
Abstract:
A connection is provided between logical macros to allow prioritization of operations in accordance with an arbitration scheme that distinguishes between operations based on such factors as priority or size of transaction. The invention allows connection of logical macros and prioritizes the appropriate operation for the resources available to optimize data throughput to optimize the utilization of multiple buses. A first arbiter manages data transmissions over a first communication bus. Arriving short or high-priority messages are transmitted over a second communication bus managed by a second arbiter, but only if the target logical macro is not the same as currently targeted by the first arbiter.

Multiple Master Inter Integrated Circuit Bus System

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US Patent:
7281070, Oct 9, 2007
Filed:
Jan 28, 2005
Appl. No.:
11/045682
Inventors:
Matthew D. Bomhoff - Tucson AZ, US
Brian J. Cagno - Tucson AZ, US
Robert A. Kubo - Tucson AZ, US
Gregg S. Lucas - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
G06F 11/00
H04J 3/24
G06F 15/16
US Classification:
710110, 709223, 713310, 713323, 713340, 710104, 370475, 714 38
Abstract:
A multiple-master Inter Integrated Circuit (“IC”) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single IC bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the IC bus. Once the first processor has initialized, the first master device acquires control of the IC bus without arbitration or interference with the second master device.

Cooling System Control With Clustered Management Services

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US Patent:
7287708, Oct 30, 2007
Filed:
Nov 12, 2004
Appl. No.:
10/988370
Inventors:
Gregg S Lucas - Tucson AZ, US
Robert A Kubo - Tucson AZ, US
Brian J Cagno - Tucson AZ, US
Matthew D Bomhoff - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
F24F 7/00
F25D 23/12
H05K 7/20
US Classification:
236 493, 622592, 361688
Abstract:
A data processing unit including a first active cooling device configured to respond to a first control signal and a second active cooling device configured to respond to a second control signal. The control signals may be any type of control signal suitable to control the operation of the first and second active cooling devices. The data processing unit also includes a first control function selectively capable of providing the first control signal and/or the second control signal, and a second control function selectively capable of providing the first control signal and/or the second control signal. Logic associated with the first and second control functions is included to determine which of the control functions will provide which control signal at a specific time. Logic and/or switching or isolation apparatus is also included to prevent both the first and second control functions from attempting to provide one of the control signals simultaneously.

Apparatus, System, And Method For Limiting Failures In Redundant Signals

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US Patent:
7337357, Feb 26, 2008
Filed:
Nov 16, 2004
Appl. No.:
10/989656
Inventors:
Brian James Cagno - Tucson AZ, US
John Charles Elliott - Tucson AZ, US
Carl Evan Jones - Tucson AZ, US
Robert Akira Kubo - Tucson AZ, US
Gregg Steven Lucas - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 14
Abstract:
An apparatus, system, and method are disclosed for limiting failures in redundant signals. A coordination module generates a power status signal for each of a plurality of power modules. An input module receives a source signal. A signal generation module generates a plurality of output signals from the source signal and at least one power status signal. The output signals are not asserted if at least one power supply is operational. If a device of the signal generation module malfunctions, no more than one output signal is erroneously asserted.

Apparatus, System, And Method For Performing Storage Device Maintenance

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US Patent:
7401260, Jul 15, 2008
Filed:
Jan 28, 2005
Appl. No.:
11/045163
Inventors:
Matthew David Bomhoff - Tucson AZ, US
Brian James Cagno - Tucson AZ, US
Gregg Steven Lucas - Tucson AZ, US
Kenny Nian Gan Qiu - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 11/00
US Classification:
714 42, 714 4, 714 5, 714 11, 714 15, 714 31
Abstract:
An apparatus, system, and method are disclosed for performing a storage device maintenance operation. A management module receives a command through an interconnection module configured as a non-blocking switch. The management module performs a maintenance operation on a storage device through the interconnection module in response to the command. In addition, the management module may receive queries on the status of the maintenance operation through the interconnection module and report the status of the maintenance operation through the interconnection module.

Apparatus And Method To Set The Signaling Rate Of A Network Disposed Within An Information Storage And Retrieval System

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US Patent:
7423964, Sep 9, 2008
Filed:
Nov 18, 2004
Appl. No.:
10/993768
Inventors:
Matthew D. Bomhoff - Tucson AZ, US
Brian J. Cagno - Tucson AZ, US
John C. Elliott - Tucson AZ, US
Carl E. Jones - Tucson AZ, US
Robert A. Kubo - Tucson AZ, US
Gregg S. Lucas - Tucson AZ, US
Katherine S. Tyldesley - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 31/08
US Classification:
370229, 37039564, 370465
Abstract:
A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.

Apparatus And Method To Set Signal Compensation Settings For A Data Storage Device

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US Patent:
7428623, Sep 23, 2008
Filed:
Jun 3, 2005
Appl. No.:
11/145386
Inventors:
Brian J. Cagno - Tucson AZ, US
Robert A. Kubo - Tucson AZ, US
Gregg S. Lucas - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 13/00
G06F 12/00
US Classification:
711167, 711100, 711112, 711154
Abstract:
A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length.

Apparatus, System, And Method For Integrating An Enclosure

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US Patent:
7519693, Apr 14, 2009
Filed:
Nov 18, 2004
Appl. No.:
10/992579
Inventors:
Matthew David Bomhoff - Tucson AZ, US
Brian James Cagno - Tucson AZ, US
John Charles Elliott - Tucson AZ, US
Robert Akira Kubo - Tucson AZ, US
Gregg Steven Lucas - Tucson AZ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 15/16
US Classification:
709220, 709228
Abstract:
An apparatus, system, and method are disclosed for integrating an enclosure. An initialization module initializes a second enclosure. A discovery module discovers a connection of the second enclosure to a first enclosure. An address module creates a valid address for the second enclosure. An assignment module assigns the address to the second enclosure. A power control module cycles power to the second enclosure to reinitialize the second enclosure and set the address.
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Brian James Cagno from Tucson, AZ, age ~49 Get Report