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Bret R Siarkowski

from Contoocook, NH
Age ~59
Get Report
Also known as:
Bret R Starkowski, Bret Siakowski, Bret I
Related to:
Bhavesh P Desai, 47
Connected to:
Edward J Siarkowicz, 78Robert D Siarski, 63Alberto Sias, 33Anna M Sias, 48Austin G Sias, 31Jill A Sias, 62Keith A Sias, 60Lorena Sias, 41Matt M Sias, 37Merced V Sias, 77

Bret Siarkowski Phones & Addresses

  • Contoocook, NH
  • Sioux Falls, SD
  • 718 Concord Rd, Marlborough, MA 01752 (508) 624-7566
  • Millbury, MA
  • Bedford, MA
  • Waltham, MA
  • Santa Monica, CA
  • 718 Concord Rd, Marlborough, MA 01752

Work

Position: Executive, Administrative, and Managerial Occupations

Education

Degree: High school graduate or higher

Emails

v***[email protected]

Business Records

Name / Title
Company / Classification
Phones & Addresses
Bret Siarkowski
President
TRIBALWIRE INC
718 Concord Rd, Marlborough, MA 01752
Lowell, MA 01852
Bret R. Siarkowski
Director
ONOVO INC
525 Mendon Rd, North Attleboro, MA 02760
281 Summer St, Boston, MA 02210
Bret Siarkowski
Founder And Chief Techni
CaseNET , Inc.
204 2 Ave, Waltham, MA 02451
(303) 601-5811
Bret Siarkowski
Limited Partner
KODIAK VENTURE PARTNERS, LIMITED PARTNERSHIP
Investment Office · Financial Advisory Services · Investment Advice
80 William St, Wellesley Hills, MA 02481
1000 Winter St, Waltham, MA 02451
100 Winter St #3800, Waltham, MA 02451
(781) 672-2500, (978) 672-2501, (781) 672-2501
Bret R Siarkowski
Director
CASENET, INC
9417 Great Hl Trl APT 2040, Austin, TX 78759
718 Concord Rd, Marlborough, MA 01752
Bret Siarkowski
Treasurer
FIREHOZE, INC
PO Box 837, Marlborough, MA 01752
718 Concord Rd, Marlborough, MA 01752
Bret R. Siarkowski
Treasurer
QUIET RIDGE, INC
718 Concord Rd, Marlborough, MA 01752
Bret Siarkowski
Manager
MARINER VENTURES IMPACT TRACER LLC
71 Isaac Davis Rd, Concord, MA 01742
718 Concord Rd, Marlborough, MA 01752

Publications

Us Patents

Method And System For False Path Analysis

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US Patent:
7216318, May 8, 2007
Filed:
Apr 29, 2004
Appl. No.:
10/836700
Inventors:
Bret Siarkowski - Marlborough MA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 4
Abstract:
Disclosed are methods and systems for performing false path analysis. In one approach, the methods and systems identify a set of zero or more false paths based upon both implementation-specific design data and non-implementation-specific design data. In some approaches, disclosed are methods and systems for performing automated gate-level static timing false path analysis, identification, constraint generation, and/or verification using architectural information. Static timing paths at the gate-level can be linked to the architectural information via mapping techniques found in equivalence checking (EC). The gate level static timing paths can be analyzed in the context of the architectural information to identify false paths.

Method And System For Logic Equivalence Checking

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US Patent:
7266790, Sep 4, 2007
Filed:
Sep 4, 2003
Appl. No.:
10/656801
Inventors:
Manish Pandey - San Jose CA, US
Yung-Te Lai - Cupertino CA, US
Bret Siarkowski - Marlborough MA, US
Chih-Chang Lin - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 1, 716 6, 716 18
Abstract:
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Method And System For Global Coverage Analysis

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US Patent:
7587690, Sep 8, 2009
Filed:
Jun 14, 2006
Appl. No.:
11/454075
Inventors:
Bret Siarkowski - Marlborough MA, US
Manish Pandey - San Jose CA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.

Method And System For False Path Analysis

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US Patent:
7958470, Jun 7, 2011
Filed:
May 7, 2007
Appl. No.:
11/745381
Inventors:
Bret Siarkowski - Marlborough MA, US
Assignee:
Cadence Design Systems, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716104, 716111, 716136, 716126
Abstract:
Disclosed are methods and systems for performing false path analysis. In one approach, the methods and systems identify a set of zero or more false paths based upon both implementation-specific design data and non-implementation-specific design data. In some approaches, disclosed are methods and systems for performing automated gate-level static timing false path analysis, identification, constraint generation, and/or verification using architectural information. Static timing paths at the gate-level can be linked to the architectural information via mapping techniques found in equivalence checking (EC). The gate level static timing paths can be analyzed in the context of the architectural information to identify false paths.

Method And System For Logic Equivalence Checking

View page
US Patent:
20070294649, Dec 20, 2007
Filed:
Aug 29, 2007
Appl. No.:
11/847177
Inventors:
Manish Pandey - San Jose CA, US
Yung-Te Lai - Cupertino CA, US
Bret Siarkowski - Marlborough MA, US
Chih-Chang Lin - San Jose CA, US
Assignee:
CADENCE DESIGN SYSTEMS, INC. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716004000
Abstract:
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Method And System For Logic Equivalence Checking

View page
US Patent:
20070294650, Dec 20, 2007
Filed:
Aug 29, 2007
Appl. No.:
11/847187
Inventors:
Manish Pandey - San Jose CA, US
Yung-Te Lai - Cupertino CA, US
Bret Siarkowski - Marlborough MA, US
Chih-Chang Lin - San Jose CA, US
Assignee:
CADENCE DESIGN SYSTEMS, INC. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716004000
Abstract:
Some embodiments relate to a method and apparatus for performing logic equivalence checking (EC) of circuits using adaptive learning based on a persistent cache containing information on sub-problems solved from previous equivalency checking runs. These sub-problems can include basic EC tasks such as logic cone comparison and/or state element mapping.

Method And System For Global Coverage Analysis

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US Patent:
20090064071, Mar 5, 2009
Filed:
Nov 10, 2008
Appl. No.:
12/267779
Inventors:
Bret SIARKOWSKI - Marlborough MA, US
Manish PANDEY - San Jose CA, US
Assignee:
CADENCE DESIGN SYSTEMS, INC. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 6
Abstract:
Disclosed are methods and systems for performing coverage analysis. In one approach, the methods and systems perform coverage analysis based upon both implementation-specific design data and non-implementation-specific design data. In an approach, both gate level and RTL level information are considered to perform coverage analysis.

Medication Storage Device And Method

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US Patent:
20130195326, Aug 1, 2013
Filed:
Jan 18, 2013
Appl. No.:
13/745175
Inventors:
Bret Siarkowski - Marlborough MA, US
Lori Donovan - Shippensburg PA, US
Assignee:
MedSentry, Inc. - Westborough MA
International Classification:
A61J 7/00
A61J 7/04
US Classification:
382128, 206534
Abstract:
Devices, systems, and methods for monitoring and enhancing patient adherence to a prescription drug regimen are disclosed herein. In some embodiments, a medication storage device includes a plurality of dose containers, each dose container having an interior region configured to contain a medication. The medication storage device also includes an event detection system that includes a plurality of sensors. The plurality of sensors are configured to detect a change in each dose container of the plurality of dose containers. The medication storage device also includes an imaging system. The imaging system includes a plurality of image capture devices configured to capture an image of the interior region of each dose container of the plurality of dose containers. A communications module is configured to send an indication of the change detected by the event detection system and/or an image captured by the imaging device to a remote device.
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Bret R Siarkowski from Contoocook, NH, age ~59 Get Report