Search

Bret R Olszewski

from Austin, TX
Age ~65
Get Report
Also known as:
Bret Ronald Olszewski, Bret P Olszewski, Bret R Olszewsi
Phone and address:
1930 Dapplegrey Ln, Austin, TX 78727
(512) 587-4177
Related to:
Henry W Detert, 96William DetertJean Detert, 63Hillary Detert, 30Garret Olszewski, 33Brit Olszewski
Connected to:
Amy J Olszewski, 48Ashley W Olszewski, 41Carl J Olszewski, 81Cynthia M Olszewski, 44Damian Olszewski, 35Daryl J Olszewski, 75Debra N Olszewski, 63Emily Olszewski, 33Hailey B Olszewski, 32Holly Olszewski, 36

Bret Olszewski Phones & Addresses

  • 1930 Dapplegrey Ln, Austin, TX 78727 (512) 587-4177
  • 10102 Spicewood Mesa, Austin, TX 78759
  • Hermantown, MN
  • Saint Paul, MN
  • 9990 Hawthorne St, Hghlnds Ranch, CO 80126
  • Highlands Ranch, CO

Resumes

Resumes

Bret Olszewski Photo 1

Bret Olszewski

View page
Location:
Austin, TX
Bret Olszewski Photo 2

Bret Olszewski

View page
Location:
Austin, TX
Industry:
Computer Software
Skills:
Aix
Db2
Virtualization
Server Architecture
Operating Systems
R
Analytics
Performance Tuning

Publications

Us Patents

Method And System For Dynamically Locating Frequently Accessed Memory Regions Or Locations

View page
US Patent:
6339818, Jan 15, 2002
Filed:
Jun 24, 1999
Appl. No.:
09/339711
Inventors:
Bret Ronald Olszewski - Austin TX
Edward Hugh Welbon - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711173, 711133
Abstract:
A method and system for monitoring the performance of a processor to detect a set of frequently accessed memory items is provided. A memory region to be monitored is selected and divided into an upper half monitored memory region and a lower half monitored memory region. Memory accesses to the upper half monitored memory region and memory accesses to the lower half monitored memory region are counted during a measurable interval. In response to the count of memory accesses to the upper half monitored memory region being greater than the count of memory accesses to the lower half monitored memory region, the monitored memory region is updated to be equal to the upper half monitored memory region. In response to the count of memory accesses to the lower half monitored memory region being greater than the count of memory accesses to the upper half monitored memory region, the monitored memory region is updated to be equal to the lower half monitored memory region. The steps of updating, dividing, and counting memory accesses to the monitored memory region during a measurable interval are repeated for a number of iterations in order to identify a frequently accessed memory region.

Method To Increase Performance Of Acquiring Free Memory Pages

View page
US Patent:
6598143, Jul 22, 2003
Filed:
Feb 24, 2000
Appl. No.:
09/513819
Inventors:
William Eugene Baker - Austin TX
Bret Ronald Olszewski - Austin TX
Jeffrey Anderson Smith - Pflugerville TX
David Blair Whitworth - Austin TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1200
US Classification:
711200, 711202, 707206
Abstract:
Initially, data is copied from a disk to a page frame and then to a read buffer, for instance. Next, a check is made to determine whether the percent of real memory occupied by file pages is less than a preset maximum volume. If so, no space is allocated for additional file page and no page frames are returned to the free list. If not, the VMM selects the best candidate file pages in real memory and returns them to the free list. Ideal candidates are a threads memory pages, from a thread doing sequential I/O the file system. In so doing, the page frames are added to the free list as soon as the I/O is complete.

Method And System For Selecting And Distinguishing An Event Sequence Using An Effective Address In A Processing System

View page
US Patent:
6708296, Mar 16, 2004
Filed:
Oct 2, 1995
Appl. No.:
08/538071
Inventors:
Frank Carl Gover - Round Rock TX
Frank Eliot Levine - Austin TX
Bret R. Olszewski - Austin TX
Charles Philip Roth - Austin TX
Edward Hugh Welbon - Austin TX
Charles Wright - Round Rock TX
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
714 47, 39518401
Abstract:
A method and system for providing a match on a selected event in performance monitoring of a processing system, the processing system including at least one performance monitor counter (PMC) is disclosed. The method and system comprises initializing the at least one PMC and controlling counting in the at least one PMC based upon the nth occurrence of a match to a specified address, where n is grater than or equal to one.

Method And System For Managing Lock Contention In A Computer System

View page
US Patent:
6845504, Jan 18, 2005
Filed:
Feb 8, 2001
Appl. No.:
09/779369
Inventors:
Hong L. Hua - Austin TX, US
Bret R. Olszewski - Austin TX, US
Mysore S. Srinivas - Austin TX, US
Nasr-Eddine Walehiane - Echirolles, FR
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 946
G06F 1200
US Classification:
718104, 718100, 718102, 718103, 710200
Abstract:
A system and method for efficiently managing lock contention for a central processing unit (CPU) of a computer system. The present invention uses both spinning and blocking (or undispatching) to manage threads when they are waiting to acquire a lock. In addition, the present invention intelligently determines when the program thread should spin and when the program thread should become undispatched. If it is determined that the program thread should become undispatched, the present invention provides efficient undispatching of program threads that improves throughput by reducing wait time to acquire the lock. A lock contention management system includes a dispatcher for managing the execution of threads on CPUs as well as threads that are currently ready to run but not executing because they are waiting for an available CPU, a dispatch management module that determines when a program thread should become undispatched to wait on a lock and when the program thread should spin, and low-priority execution module for undispatching the program thread. The present invention also includes a lock contention management method using the above system.

System And Method For Improving Performance Of Dynamic Memory Removals By Reducing File Cache Size

View page
US Patent:
7240177, Jul 3, 2007
Filed:
May 27, 2004
Appl. No.:
10/855847
Inventors:
David Alan Hepkin - Austin TX, US
Bret Ronald Olszewski - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/00
US Classification:
711173, 711159, 711129, 711133
Abstract:
A system and method for improving dynamic memory removals by reducing the file cache size prior to the dynamic memory removal operation initiating are provided. In one exemplary embodiment, the maximum amount of physical memory that can be used to cache files is reduced prior to performing a dynamic memory removal operation. Reducing the maximum amount of physical memory that can be used to cache files causes the page replacement algorithm to aggressively target file pages to bring the size of the file cache below the new maximum limit on the file cache size. This results in more file pages, rather than working storage pages, being paged-out.

Method For Graphical Display Of Cpu Utilization

View page
US Patent:
7460122, Dec 2, 2008
Filed:
Feb 22, 2008
Appl. No.:
12/035800
Inventors:
Luc R. Smolders - Rochester MN, US
Bret R. Olszewski - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06T 11/20
US Classification:
345440
Abstract:
A method for graphically displaying central processing unit consumption for at least one variable capacity or uncapped partition including displaying CPU utilization or consumption of at least one variable capacity or uncapped partition in a variable-size colored pie chart. The pie chart shows time spent in at least one of user mode, operating system mode, I/O wait mode, or idle mode, with each mode being represented by a different color. An entitlement indicator is displayed for the effective minimum capacity of the at least one variable capacity or uncapped partition.

Method And Apparatus For Supporting Shared Library Text Replication Across A Fork System Call

View page
US Patent:
7469331, Dec 23, 2008
Filed:
Jul 22, 2004
Appl. No.:
10/897329
Inventors:
David Alan Hepkin - Austin TX, US
Bret Ronald Olszewski - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 9/26
US Classification:
711202, 719312
Abstract:
A fork system call by a first process is detected. A second process is created as a replication of the first process with a second affinity. If a replication of the replicated shared library is present in the second affinity domain, effective addresses of the replication of the replicated shared library are mapped using a mapping mechanism of the present invention to physical addresses in the second affinity domain.

Method And Apparatus For Tracking Variable Speed Microprocessor Performance Caused By Power Management In A Logically Partitioned Data Processing System

View page
US Patent:
7543161, Jun 2, 2009
Filed:
Sep 30, 2004
Appl. No.:
10/955182
Inventors:
Bret Ronald Olszewski - Austin TX, US
Luc Rene Smolders - Austin TX, US
Randal Craig Swanberg - Round Rock TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1/00
US Classification:
713300, 702 61
Abstract:
A power level monitor and performance tracking tool are provided for correlating system performance with processor management events. When power management requires a change to the state of a microprocessor, software will be notified. Multiple layers of software may be notified, including a firmware level, an operating system, as well as applications. The performance tracking tool tracks the times of the power management events as well as their impact to the microprocessor performance. The performance tracking tool may then display or record the state changes to processor performance. These changes may be correlated against other system events to aid in determining system performance problems with respect to power management.
Control profile
Bret R Olszewski from Austin, TX, age ~65 Get Report