Brent M Roberts

7629680, Dec 8, 2009

Mar 22, 2006

11/387512

Brent M. Roberts - Phoenix AZ, US
Sriram Srinivasan - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 23/52

257691

In some embodiments, direct power delivery into an electronic package is presented. In this regard, a substrate is introduced having a conductive substrate core designed to physically connect with a power cable. Other embodiments are also disclosed and claimed.

8278752, Oct 2, 2012

Dec 23, 2009

12/646854

Brent M. Roberts - Phoenix AZ, US
Mihir K. Roy - Chandler AZ, US
Sriram Srinivasan - Chandler AZ, US
Sridhar Narasimhan - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 23/34
H01L 23/48

257726, 257723, 257696, 257692, 257697, 257698, 257E23146

A microelectronic package includes first substrate () having first surface area () and second substrate () having second surface area (). The first substrate includes first set of interconnects () having first pitch () at first surface () and second set of interconnects () having second pitch () at second surface (). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects () having third pitch () and internal electrically conductive layers () connected to each other with microvia (). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

8381393, Feb 26, 2013

Dec 30, 2009

12/655406

Brent M. Roberts - Phoenix AZ, US
Mihir K. Roy - Chandler AZ, US
Sriram Srinivasan - Chandler AZ, US
Sridhar Narasimhan - Chandler CA, US

Intel Corporation - Santa Clara CA

H01K 3/10

29825, 257696, 257726

Methods of forming a microelectronic structure are described. Embodiments of those methods include attaching a patch to an interposer, forming at least one interconnect structure above and on a top surface of the interposer; and attaching a flex connector to the at least one interconnect structure.

8389337, Mar 5, 2013

Dec 31, 2009

12/655588

Brent M. Roberts - Phoenix AZ, US
Mihir K. Roy - Chandler AZ, US
Sriram Srinivasan - Phoenix AZ, US

Intel Corporation - Santa Clara CA

H01L 23/60

438124, 438118, 438121, 438126, 438E21506

Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.

8440506, May 14, 2013

Jul 11, 2012

13/546549

Brent M. Roberts - Phoenix AZ, US
Mihir K. Roy - Chandler AZ, US
Sriram Sriniyasan - Chandler AZ, US
Sridhar Narasimhan - Chandler AZ, US

Intel Corporation - Santa Clara CA

H01L 21/44
H01L 21/48

438117, 438107, 438109, 257E21506

A microelectronic package includes first substrate () having first surface area () and second substrate () having second surface area (). The first substrate includes first set of interconnects () having first pitch () at first surface () and second set of interconnects () having second pitch () at second surface (). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects () having third pitch () and internal electrically conductive layers () connected to each other with microvia (). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

20110108947, May 12, 2011

Nov 12, 2009

12/590650

John S. Guzek - Chandler AZ, US
Mihir K. Roy - Chandler AZ, US
Brent M. Roberts - Phoenix AZ, US

H01L 23/48
H01L 21/768

257531, 438107, 257773, 257E21575, 257E2301

A microelectronic device comprises a first substrate () having a first electrically conductive path () therein and a second substrate () above the first substrate and having a second electrically conductive path () therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop () of an inductor ().

20130141859, Jun 6, 2013

Jan 30, 2013

13/753863

Brent M. Roberts - Phoenix AZ, US
Mihir K. Roy - Chandler AZ, US
Sriram Srinivasan - Chandler AZ, US

H05K 1/11
G06F 1/18

36167931, 174263

Methods of forming microelectronic structures are described. Embodiments of those methods include attaching a patch structure to an interposer by thermal compression bonding, forming an underfill around an array of interconnect structures disposed on a top surface of the interposer, curing the underfill, and then attaching a die to the patch structure.