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Brennen K Mueller

from Austin, TX
Age ~36
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Also known as:
Brennen Nicolle Mueller
Related to:
Nicolle S MuellerAustin Mueller BriceKendall Mueller, 30Brice Mueller, 35
Connected to:
Absaloom Mueller, 46Aino E Mueller, 41Amy S Mueller, 60Angelina Mueller, 107Armin C Mueller, 92Arnd Mueller, 58Ashley L Mueller, 41Benito Mueller, 48Beverlee K Mueller, 66Birgit Mueller, 71

Brennen Mueller Phones & Addresses

  • Austin, TX
  • Portland, OR
  • Beaverton, OR
  • Atlanta, GA
  • Nipomo, CA
  • Pismo Beach, CA
  • Corona, CA
  • North Richland Hills, TX

Work

Company: Intel corporation Sep 2019 Position: Quantum computing integration engineer

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Georgia Institute of Technology 2010 to 2014 Specialities: Chemical Engineering

Skills

Chemical Engineering • Matlab • Polymers • Photolithography • Design of Experiments • Lithography • Microsoft Office • Chemistry • Microelectronics • R&D • Chemical Characterization

Industries

Semiconductors

Resumes

Resumes

Brennen Mueller Photo 1

Quantum Computing Integration Engineer

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Location:
19750 northwest Phillips Rd, Hillsboro, OR 97124
Industry:
Semiconductors
Work:
Intel Corporation
Quantum Computing Integration Engineer
Intel Corporation Mar 2015 - Sep 2019
Senior R and D Process Engineer
Georgia Institute of Technology Aug 2010 - Dec 2014
Ph.d Candidate and Intel Foundation and Senior Cea Graduate Fellow
Intel Corporation May 2014 - Aug 2014
Graduate Intern
Applied Materials May 2013 - Aug 2013
Associate Intern
Education:
Georgia Institute of Technology 2010 - 2014
Doctorates, Doctor of Philosophy, Chemical Engineering The University of Texas at Austin 2006 - 2010
Bachelors, Bachelor of Science, Chemical Engineering
Skills:
Chemical Engineering
Matlab
Polymers
Photolithography
Design of Experiments
Lithography
Microsoft Office
Chemistry
Microelectronics
R&D
Chemical Characterization

Publications

Us Patents

Silicon-Containing Block Co-Polymers, Methods For Synthesis And Use

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US Patent:
20130196019, Aug 1, 2013
Filed:
Mar 17, 2011
Appl. No.:
13/583369
Inventors:
C. Grant Willson - Austin TX, US
Christopher M. Bates - Austin TX, US
Jeffrey Strahan - Austin TX, US
Christopher John Ellison - Austin TX, US
Brennen Mueller - Atlanta GA, US
Assignee:
National University of Sinapore - Singapore
International Classification:
B05D 3/10
H01L 21/02
US Classification:
425470, 216 11
Abstract:
The present invention describes the synthesis of silicon-containing monomers and copolymers. The synthesis of a monomer, trimethyl-(2-methylenebut-3-enyl)silane (TMSI) and subsequent synthesis of diblock copolymer with styrene, forming polystyrene-block-polytrimethylsilyl isoprene, and synthesis of diblock copolymer Polystyrene-block-polymethacryloxymethyltrimethylsilane or PS-b-P(MTMSMA). These silicon containing diblock copolymers have a variety of uses. One preferred application is as novel imprint template material with sub-100 nm features for lithography.

Interconnect Structures And Methods Of Fabrication

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US Patent:
20220336267, Oct 20, 2022
Filed:
Jun 27, 2022
Appl. No.:
17/850876
Inventors:
- Santa Clara CA, US
Ramanan Chebiam - Hillsboro OR, US
Brennen Mueller - Portland OR, US
Colin Carver - Hillsboro OR, US
Jeffery Bielefeld - Forest Grove OR, US
Nafees Kabir - Portland OR, US
Richard Vreeland - Beaverton OR, US
William Brezinski - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/768
H01L 23/528
H01L 23/535
H01L 23/00
H04B 1/40
Abstract:
An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

Microelectronic Assemblies

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US Patent:
20220278057, Sep 1, 2022
Filed:
May 19, 2022
Appl. No.:
17/748877
Inventors:
- Santa Clara CA, US
Patrick Morrow - Portland OR, US
Henning Braunisch - Phoenix AZ, US
Kimin Jun - Portland OR, US
Brennen Karl Mueller - Portland OR, US
Shawna M. Liff - Scottsdale AZ, US
Johanna M. Swan - Scottsdale AZ, US
Paul B. Fischer - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/64
H01L 23/34
H01L 23/66
H01L 49/02
Abstract:
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

Microelectronic Assemblies

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US Patent:
20220254754, Aug 11, 2022
Filed:
Apr 25, 2022
Appl. No.:
17/728813
Inventors:
- Santa Clara CA, US
Henning BRAUNISCH - Phoenix AZ, US
Aleksandar ALEKSOV - Chandler AZ, US
Shawna M. LIFF - Scottsdale AZ, US
Johanna M. SWAN - Scottsdale AZ, US
Patrick MORROW - Portland OR, US
Kimin JUN - Portland OR, US
Brennen MUELLER - Portland OR, US
Paul B. FISCHER - Portland OR, US
International Classification:
H01L 25/065
H01L 23/498
H01L 25/00
Abstract:
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

Sacrificial Redistribution Layer In Microelectronic Assemblies Having Direct Bonding

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US Patent:
20230074970, Mar 9, 2023
Filed:
Nov 9, 2022
Appl. No.:
18/053869
Inventors:
- Santa Clara CA, US
Veronica Aleman Strong - Hillsboro OR, US
Shawna M. Liff - Scottsdale AZ, US
Brandon M. Rawlings - Chandler AZ, US
Jagat Shakya - Hillsboro OR, US
Johanna M. Swan - Scottsdale AZ, US
David M. Craig - Hillsboro OR, US
Jeremy Alan Streifer - Beaverton OR, US
Brennen Karl Mueller - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/00
B81B 7/00
Abstract:
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

Gate-All-Around Integrated Circuit Structures Having Strained Dual Nanoribbon Channel Structures

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US Patent:
20210407996, Dec 30, 2021
Filed:
Jun 26, 2020
Appl. No.:
16/913333
Inventors:
Ashish AGRAWAL - Hillsboro OR, US
Brennen MUELLER - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US
Jessica TORRES - Portland OR, US
Kimin JUN - Portland OR, US
Siddharth CHOUKSEY - Portland OR, US
Willy RACHMADY - Beaverton OR, US
Koustav GANGULY - Beaverton OR, US
Ryan KEECH - Portland OR, US
Matthew V. METZ - Portland OR, US
Anand S. MURTHY - Portland OR, US
International Classification:
H01L 27/092
H01L 29/06
H01L 29/423
H01L 29/78
H01L 29/786
H01L 21/02
H01L 21/8238
H01L 29/66
Abstract:
Gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. Individual ones of the first vertical arrangement of nanowires are biaxially tensilely strained. The integrated circuit structure also includes a second vertical arrangement of nanowires above the substrate. Individual ones of the second vertical arrangement of nanowires are biaxially compressively strained. The individual ones of the second vertical arrangement of nanowires are laterally staggered with the individual ones of the first vertical arrangement of nanowires.

Nterconnect Structures And Methods Of Fabrication

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US Patent:
20210098360, Apr 1, 2021
Filed:
Sep 27, 2019
Appl. No.:
16/586279
Inventors:
- Santa Clara CA, US
Ramanan Chebiam - Hillsboro OR, US
Brennen Mueller - Portland OR, US
Colin Carver - Hillsboro OR, US
Jeffery Bielefeld - Forest Grove OR, US
Nafees Kabir - Portland OR, US
Richard Vreeland - Beaverton OR, US
William Brezinski - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/528
H01L 23/535
H01L 23/00
H04B 1/40
Abstract:
An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

Metallization Barrier Structures For Bonded Integrated Circuit Interfaces

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US Patent:
20210098387, Apr 1, 2021
Filed:
Sep 27, 2019
Appl. No.:
16/585666
Inventors:
- Santa Clara CA, US
Mauro Kobrinsky - Portland OR, US
Richard Vreeland - Beaverton OR, US
Ramanan Chebiam - Hillsboro OR, US
William Brezinski - Beaverton OR, US
Brennen Mueller - Portland OR, US
Jeffery Bielefeld - Forest Grove OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 23/532
H01L 21/768
Abstract:
Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.
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Brennen K Mueller from Austin, TX, age ~36 Get Report