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Brad J Garni

from Austin, TX
Age ~66
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Also known as:
Bradley J Garni, Bradley John Garni, Bradley G Garni, Bradley L Garni, Bradley I
Phone and address:
4532 Eagle Feather Dr, Austin, TX 78735
(512) 899-2740
Related to:
Tyler M Garni, 35Olivia Gena Garni, 31Tessa GarniShelly Garni, 64
Connected to:
Adan Z Garnica, 49Albert D Garnica, 56Alvaro Garnica, 53Ann T Garnica, 60Cinthya Garnica, 36Dora Garnica, 76Elvira C Garnica, 59Emmanuel Garnica, 35Erica Garnica, 37Evelyn J Garnica, 35

Brad Garni Phones & Addresses

  • 4532 Eagle Feather Dr, Austin, TX 78735 (512) 899-2740
  • New Berlin, WI
  • 1237 Spaight St, Madison, WI 53703 (608) 258-8503
  • Dyer, TN

Work

Company: Freescale semiconductor Sep 2012 Position: Senior am design manager

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Wisconsin - Madison Specialities: Materials Science, Engineering

Skills

Cmos • Semiconductors • Soc • Ic • Silicon • Physical Design • Process Integration • Embedded Systems • Sram • Eda • Asic • Microelectronics • Semiconductor Industry • Mixed Signal • Drc • Simulations • Analog • Design of Experiments • Integrated Circuit Design • Product Engineering • Vlsi • Functional Verification • R&D • Semiconductor Process • Rtl Design • Physical Verification • Low Power Design • Dft

Industries

Semiconductors

Resumes

Resumes

Brad Garni Photo 1

Senior Am Design Manager

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Freescale Semiconductor
Senior Am Design Manager
Freescale Semiconductor Aug 2007 - Sep 2012
Project Lead Memory Design Engineer
Freescale Semiconductor Jul 2006 - Aug 2007
Memory Design Expert
Freescale Semiconductor 1999 - Jul 2006
Senior Memory Design Engineer
Motorola 1997 - 1999
Process Development
Education:
University of Wisconsin - Madison
Doctorates, Doctor of Philosophy, Materials Science, Engineering
Skills:
Cmos
Semiconductors
Soc
Ic
Silicon
Physical Design
Process Integration
Embedded Systems
Sram
Eda
Asic
Microelectronics
Semiconductor Industry
Mixed Signal
Drc
Simulations
Analog
Design of Experiments
Integrated Circuit Design
Product Engineering
Vlsi
Functional Verification
R&D
Semiconductor Process
Rtl Design
Physical Verification
Low Power Design
Dft

Publications

Us Patents

Balanced Load Memory And Method Of Operation

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US Patent:
6711068, Mar 23, 2004
Filed:
Jun 28, 2002
Appl. No.:
10/184720
Inventors:
Chitra K. Subramanian - Austin TX
Brad J. Garni - Austin TX
Joseph J. Nahas - Austin TX
Halbert S. Lin - Austin TX
Thomas W. Andre - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 700
US Classification:
36518902, 365210, 36523003
Abstract:
A memory provides a sensing scheme that maintains impedance balance between the route that the data takes to the sense amplifier and the route the reference or references take to the sense amplifier. Each sub-array of the memory has an adjacent column decoder that couples data to a data line that is also adjacent to the sub-array and may be considered part of the column decoder. The data for the selected sub-array is routed to the sense amplifier via its adjacent data line. The reference that is part of the selected sub-array is coupled to the data line of a non-selected sub-array. Thus the reference, which in the case of a MRAM type memory is preferably in close proximity to the location of the selected data, traverses a route to the sense amplifier that is impedance balanced with respect to the route taken by the data.

Circuit And Method For Reading A Toggle Memory Cell

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US Patent:
6744663, Jun 1, 2004
Filed:
Jun 28, 2002
Appl. No.:
10/184811
Inventors:
Brad J. Garni - Austin TX
Thomas W. Andre - Austin TX
Joseph J. Nahas - Austin TX
Chitra K. Subramanian - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 1115
US Classification:
365171, 365158, 365173
Abstract:
A MRAM toggle type memory cell is read by first providing a first signal representative of the initial state to a sense amplifier ( ). A resistance of the cell is temporarily changed by altering a magnetic polarization of the free layer of the cell. A second signal responsive to altering the resistance of the MRAM cell is provided to the sense amplifier ( ). The first signal is compared to the second signal to determine the state of the MRAM cell.

Sense Amplifier With Multiple Bits Sharing A Common Reference

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US Patent:
7292484, Nov 6, 2007
Filed:
Jun 7, 2006
Appl. No.:
11/422774
Inventors:
Thomas W. Andre - Austin TX, US
Brad J. Garni - Austin TX, US
Joseph J. Nahas - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 5/14
G11C 7/10
G11C 7/06
G11C 7/02
US Classification:
36518909, 36518903, 36518905, 36518907, 365207
Abstract:
A memory circuit includes a sense amplifier in which a single reference signal is compared to two data signals from two memory cells. The reference signal is generated from the combination of memory cells in opposite logic states. The data signal capacitance is matched to the reference signal capacitance. With reduced but matched capacitance both high speed and high sensitivity can be achieved.

Memory Circuit With Sense Amplifier

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US Patent:
7881138, Feb 1, 2011
Filed:
Jul 10, 2006
Appl. No.:
12/373184
Inventors:
Brad Garni - Austin TX, US
Thomas Andre - Austin TX, US
Jean Lasseuguette - Grenoble, FR
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 7/06
US Classification:
365207, 365208, 365209
Abstract:
A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal.

Circuit And Method Of Writing A Toggle Memory

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US Patent:
20040001352, Jan 1, 2004
Filed:
Jun 28, 2002
Appl. No.:
10/186141
Inventors:
Joseph Nahas - Austin TX, US
Thomas Andre - Austin TX, US
Chitra Subramanian - Austin TX, US
Brad Garni - Austin TX, US
International Classification:
G11C011/00
US Classification:
365/158000
Abstract:
A magnetoresistive random access memory is operated in a toggle fashion so that its logic state is flipped from its current state to the alternate state when written. This provides for a more consistent and reliable programming because the magnetic transitional energy states during the toggle operation are stable. In a write situation, however, this does mean that the state of the cell must be read and compared to the desired state of the cell before the cell is flipped. If the cell is already in the desired logic state, then it should not be written. This read time penalty before writing is reduced by beginning the write process while reading and then aborting the write step if the cell is already in the desired state. The write can actually begin on the cell and be aborted without adversely effecting the state of the cell.

Single-Event Latch-Up Prevention Techniques For A Semiconductor Device

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US Patent:
20140027810, Jan 30, 2014
Filed:
Jul 27, 2012
Appl. No.:
13/560010
Inventors:
Jianan Yang - Austin TX, US
James D. Burnett - Austin TX, US
Brad J. Garni - Austin TX, US
Thomas W. Liston - Austin TX, US
Huy Van Pham - Cedar Park TX, US
Assignee:
FREESCALE SEMICONDUCTOR, INC. - Austin TX
International Classification:
H01L 27/06
G06F 17/50
US Classification:
257133, 716110, 257E27015
Abstract:
A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power supply node and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor includes a first terminal coupled to the first power supply node, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor is not positioned between a base of the pnp BJT and the first power supply node. The first transistor limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.

Data Processing System And Method For Generating A Digital Code With A Physically Unclonable Function

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US Patent:
20210027814, Jan 28, 2021
Filed:
Jul 26, 2019
Appl. No.:
16/523284
Inventors:
- AUSTIN TX, US
Alexander Hoefler - Austin TX, US
Brad John Garni - Austin TX, US
International Classification:
G11C 7/12
G11C 11/419
G11C 11/418
G11C 7/18
H04L 9/32
Abstract:
A data processing system and method for generating a digital code for use as a physically unclonable function (PUF) response is provided. The method includes activating a plurality of word lines for a read operation. A first bit line is coupled to a first input of a comparator during the read operation. A second bit line is coupled to a second input of the comparator during the read operation. A current is generated on each of the first and second bit lines. The currents on the first and second bit lines are converted to voltages. The voltage on the first bit line is compared to the voltage on the second bit line. A logic bit is output from the comparator as part of the digital code, a logic state of the logic bit is determined in response to the comparison. By selecting multiple word lines to determine a PUF response, noise immunity is improved.

Memory Array With Read Only Cells Having Multiple States And Method Of Programming Thereof

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US Patent:
20160172052, Jun 16, 2016
Filed:
Dec 10, 2014
Appl. No.:
14/565875
Inventors:
- AUSTIN TX, US
BRAD J. GARNI - AUSTIN TX, US
SHAYAN ZHANG - CEDAR PARK TX, US
International Classification:
G11C 17/12
Abstract:
A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.
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Brad J Garni from Austin, TX, age ~66 Get Report