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Boris Murmann

from Honolulu, HI
Age ~54
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Related to:
Yukiko Murmann, 55
Connected to:
Anja Murmann, 62Emily R Murn, 30Sheila H Murnaghan, 73Evan M Murnan, 42Matthew L Murnan, 38Shaun P Murnan, 45Tad W Murnan, 55Donald M Murnane, 97Kara Murnane, 38Sandi S Murnane, 55

Boris Murmann Phones & Addresses

  • Honolulu, HI
  • 351 Olmsted Rd, Stanford, CA 94305
  • Palo Alto, CA
  • 1397 Ada St, Berkeley, CA 94702 (510) 524-4311
  • 1040 Clay St, Albany, CA 94706
  • Pacifica, CA
  • Emeryville, CA
  • Cupertino, CA

Resumes

Resumes

Boris Murmann Photo 1

Professor

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Location:
San Francisco, CA
Industry:
Higher Education
Work:
Stanford University since Sep 2010
Associate Professor
Stanford University Jan 2004 - Aug 2010
Assistant Professor
Education:
University of California, Berkeley 1999 - 2003
PhD, Electrical Engineering Santa Clara University 1997 - 1999
MS, Electrical Engineering
Skills:
Mixed Signal
Integrated Circuit Design
Analog Circuit Design
Simulations
Cmos
Sensors
Circuit Design
Matlab
Semiconductors
Signal Processing
Ic
Verilog
Analog
Vlsi
Mems
Cadence Virtuoso
Digital Signal Processors
Asic
Fpga
Electronics
Eda
Soc
Rf
Computer Architecture
Integrated Circuits
Characterization
Electrical Engineering
Digital Electronics
System on A Chip
Atmel Avr
Raspberry Pi
Field Programmable Gate Arrays
Interests:
Mixed Signal Integrated Circuit Design
Digital To Analog Converters
Sensor Interfaces
Analog To Digital Converters
Languages:
German
Boris Murmann Photo 2

Associate Professor At Stanford University

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Position:
Associate Professor at Stanford University
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
Stanford University since Sep 2010
Associate Professor
Stanford University Jan 2004 - Aug 2010
Assistant Professor
Education:
University of California, Berkeley 1999 - 2003
PhD, Electrical Engineering Santa Clara University 1997 - 1999
MS, Electrical Engineering
Skills:
CMOS
Analog Circuit Design
Integrated Circuit Design
Mixed Signal
Circuit Design
Sensors
IC
Interests:
Mixed-signal integrated circuit design Analog-to-digital converters Digital-to-analog converters Sensor interfaces

Publications

Us Patents

Method And System For Fet-Based Amplifier Circuits

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US Patent:
7482864, Jan 27, 2009
Filed:
Jan 31, 2007
Appl. No.:
11/700372
Inventors:
Boris Murmann - Palo Alto CA, US
Jason C. Hu - Cupertino CA, US
Assignee:
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
International Classification:
H03F 1/02
US Classification:
330 9
Abstract:
Amplifier circuits and methods are implemented using a variety of different embodiments. According to one such embodiment, an amplifier circuit is implemented to amplify a first signal to drive an output load. The circuit has a field-effect transistor (FET) with a gate, a source and a drain. A switch arrangement is coupled to the gate, the source and the drain. State control logic provides state information for a first state and a second state. In the first state, the first switch arrangement connects the first signal to the gate and connects the drain and source to reference voltages. In the second state, the switch arrangement disconnects the first signal from the gate, connects the drain to a voltage supply and connects the source to the output load, thereby causing the FET to operate in source-follower mode.

Method And System For Fet-Based Amplifier Circuits

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US Patent:
7791410, Sep 7, 2010
Filed:
Oct 29, 2008
Appl. No.:
12/260925
Inventors:
Boris Murmann - Palo Alto CA, US
Jason C. Hu - Cupertino CA, US
Assignee:
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
International Classification:
H03F 1/02
US Classification:
330 9
Abstract:
Amplifier circuits and methods are implemented using a variety of different embodiments. According to one such embodiment, a method is implemented using a field-effect transistor (FET) having a gate node, a source node and a drain node. A first circuit state is implemented in which the gate node, the source node and the drain node are connected to inputs that generate a stored charge at the gate node, the amount of stored charge at the gate node being responsive to a first voltage level. A second circuit state is implemented in which the drain node is connected to a voltage source, the source node is connected to a load, and while charge at the gate node is preserved, current between the drain node to the source node drives a voltage level of the load to a proportionally amplified version of the first voltage level.

Method And System For Driver Circuits Of Capacitive Loads

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US Patent:
7369080, May 6, 2008
Filed:
Sep 14, 2006
Appl. No.:
11/521077
Inventors:
Echere Iroaga - Mountain View CA, US
Boris Murmann - Palo Alto CA, US
Assignee:
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
International Classification:
H03M 1/12
US Classification:
341172, 341161, 320166
Abstract:
Driver circuits for switched-capacitor circuits are implemented using a variety of methods and devices. According to one such circuit, a switched-capacitor driver circuit is implemented for producing an output signal by driving a capacitive output load in response to step input signals. The driver circuit includes output circuitry that drives the capacitive output load toward a steady-state mode responsive to one of the step input signals and control circuitry that, before realizing the steady-state mode, inhibits the output circuitry from driving the capacitive output load to the steady-state mode.

Arrangements And Methods For Providing Compensation For Non-Idealities Of Components In Communications Systems

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US Patent:
8290031, Oct 16, 2012
Filed:
Aug 14, 2007
Appl. No.:
11/838566
Inventors:
Boris Murmann - Palo Alto CA, US
Yangjin Oh - Palo Alto CA, US
Assignee:
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA
International Classification:
H04B 3/46
H04B 17/00
H04Q 1/20
US Classification:
375224, 375285, 370241, 370491, 370500
Abstract:
For use in or as part of a communications system benefiting from compensation for one or more non-idealities of components in the communications system, aspects of the invention are directed to providing compensation for such non-idealities. An example method which is applicable in a system that receives a pilot signal having an expected amplitude, includes determining a received amplitude for the received pilot signal using at least one of the components of the communications system, and using feedback indicative of a comparison of the determined received amplitude and the expected amplitude, compensating for a non-ideality of the component.

Filtering Circuit With Jammer Generator

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US Patent:
8351842, Jan 8, 2013
Filed:
May 22, 2012
Appl. No.:
13/477552
Inventors:
Shinichi Hori - Tokyo, JP
Boris Murmann - Palo Alto CA, US
Assignee:
NEC Corporation - Tokyo
The Board of Trustees of the Leland Stanford Junior University - Stanford CA
International Classification:
H04K 3/00
US Classification:
455 1, 455 631, 455296, 455501
Abstract:
A filtering circuit with a jammer generator cancels a jammer in wireless signals with little degradation of the signal-to-noise ratio (SNR). The filtering circuit may include a jammer generator which acquires information of period and phase of a sinusoidal jammer signal in a composite input sinusoidal signal, which includes the jammer signal and a desired signal, and outputs a pseudo sine-wave with a period and phase corresponding with the period and phase of the jammer signal acquired, and an adder which outputs a difference between the input and output signals of the jammer generator as the desired signal.

Filtering Circuit With Jammer Generator

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US Patent:
8208849, Jun 26, 2012
Filed:
Apr 29, 2009
Appl. No.:
12/432196
Inventors:
Shinichi Hori - Minato-ku, JP
Boris Murmann - Palo Alto CA, US
Assignee:
NEC Corporation - Tokyo
The Board of Trustees of the Leland Stanford Junior University - Stanford CA
International Classification:
H04K 3/00
US Classification:
455 1, 455 631, 4551142, 455501
Abstract:
A filtering circuit with a jammer generator cancels a jammer in wireless signals with little degradation of the signal-to-noise ratio (SNR). The filtering circuit may include a jammer generator which acquires information of period and phase of a sinusoidal jammer signal in a composite input sinusoidal signal, which includes the jammer signal and a desired signal, and outputs a pseudo sine-wave with a period and phase corresponding with the period and phase of the jammer signal acquired, and an adder which outputs a difference between the input and output signals of the jammer generator as the desired signal.

Mesoscale System Feedback-Induced Dissipation And Noise Suppression

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US Patent:
20210341404, Nov 4, 2021
Filed:
May 11, 2021
Appl. No.:
17/317422
Inventors:
- Stanford CA, US
Ross M. Walker - Salt Lake City UT, US
Boris Murmann - Stanford CA, US
Roger T. Howe - Stanford CA, US
International Classification:
G01N 27/02
G01N 27/327
G01N 27/416
G01N 27/49
Abstract:
A high-gain and low-noise negative feedback control (“feedback control”) system can detect charge transfer in quantum systems at room temperatures. The feedback control system can attenuate dissipative coupling between a quantum system and its thermodynamic environment. The feedback control system can be integrated with standard commercial voltage-impedance measurement system, for example, a potentiostat. In one aspect, the feedback control system includes a plurality of electrodes that are configured to electrically couple to a sample, and a feedback mechanism coupled to a first electrode of the plurality of electrodes. The feedback mechanism is configured to detect a potential associated with the sample via the first electrode. The feedback mechanism provides a feedback signal to the sample via a second electrode of the plurality of electrodes, the feedback signal is configured to provide excitation control of the sample at a third electrode of the plurality of electrode.
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Boris Murmann from Honolulu, HI, age ~54 Get Report