Professional Records
License Records
Binoy Vidyasagar
Address:
1113 Alder Way, Longmont, CO 80503
License #:
A5157072
Category:
Airmen
Binoy Vidyasagar Phones & Addresses
-
Longmont, CO
Work
Company:
Avago technologies Dec 2013 to May 2015
Position:
Senior asic design engineer
Education
Degree:
Bachelor of Engineering, Bachelors
School / High School:
Bharathiar University College of Arts and Science 1998 to 2002
Specialities:
Communications, Communication, Engineering, Electronics
Skills
Asic • Static Timing Analysis • Physical Design • Vlsi • Timing Closure • Very Large Scale Integration • System on A Chip • Verilog • Physical Verification • Formal Verification • Floorplanning • Drc • Lvs • Tcl • Magma • Cadence • Synopsys • Primetime • Timing • Power Analysis • Functional Verification • Layout Versus Schematic • Design Rule Checking • Eda • Integrated Circuit Design • Place and Route • Semiconductors
Industries
Semiconductors
Resumes
Resumes
Senior Ic Design Engineer
View pageLocation:
1320 Ridder Park Dr, San Jose, CA 95131
Industry:
Semiconductors
Work:
Avago Technologies Dec 2013 - May 2015
Senior Asic Design Engineer
Broadcom Dec 2013 - May 2015
Senior Ic Design Engineer
Lsi Corporation Oct 2012 - Dec 2013
Senior Asic Development and Design Engineer at Lsi Corporation
Lsi Corporation Jul 2011 - Sep 2012
Senior Asic Customer Engineer
Wipro Technologies Aug 2005 - Jul 2011
Project Leader
Senior Asic Design Engineer
Broadcom Dec 2013 - May 2015
Senior Ic Design Engineer
Lsi Corporation Oct 2012 - Dec 2013
Senior Asic Development and Design Engineer at Lsi Corporation
Lsi Corporation Jul 2011 - Sep 2012
Senior Asic Customer Engineer
Wipro Technologies Aug 2005 - Jul 2011
Project Leader
Education:
Bharathiar University College of Arts and Science 1998 - 2002
Bachelor of Engineering, Bachelors, Communications, Communication, Engineering, Electronics
Bachelor of Engineering, Bachelors, Communications, Communication, Engineering, Electronics
Skills:
Asic
Static Timing Analysis
Physical Design
Vlsi
Timing Closure
Very Large Scale Integration
System on A Chip
Verilog
Physical Verification
Formal Verification
Floorplanning
Drc
Lvs
Tcl
Magma
Cadence
Synopsys
Primetime
Timing
Power Analysis
Functional Verification
Layout Versus Schematic
Design Rule Checking
Eda
Integrated Circuit Design
Place and Route
Semiconductors
Static Timing Analysis
Physical Design
Vlsi
Timing Closure
Very Large Scale Integration
System on A Chip
Verilog
Physical Verification
Formal Verification
Floorplanning
Drc
Lvs
Tcl
Magma
Cadence
Synopsys
Primetime
Timing
Power Analysis
Functional Verification
Layout Versus Schematic
Design Rule Checking
Eda
Integrated Circuit Design
Place and Route
Semiconductors