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Beth A Rainey

from Pottersville, NJ
Age ~74
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Also known as:
Beth Ann Rainey, Elizabeth Rainey, Beth Rainy
Related to:
John A Boose
Connected to:
Adrian Rainey, 50Allyson S Rainey, 41Bartow B Rainey, 61Benjamin E Rainey, 75Bonnie L Rainey, 83Bradtric D Rainey, 47Breanna A Rainey, 32Bree P Rainey, 39Brooke R Rainey, 44Buddy A Rainey, 48

Beth Rainey Phones & Addresses

  • Pottersville, NJ
  • Millerton, NY
  • Litchfield, CT
  • 39 Main St S, Bethlehem, CT 06751
  • 4 North St, Enola, PA 17025 (717) 728-9129
  • New Cumberlnd, PA
  • New Cumberlnd, PA
  • Harrisburg, PA

Work

Company: Prudential/detrick realty Address: 38 Cranbury Station Road, East Windsor, NJ 08512 Phones: (918) 746-6000 Position: Coo Industries: Real Estate Agents and Managers

Business Records

Name / Title
Company / Classification
Phones & Addresses
Beth Rainey
COO
Prudential/detrick Realty
Real Estate Agents and Managers
38 Cranbury Station Road, East Windsor, NJ 08512
Beth Rainey
COO
Prudential/detrick Realty
Real Estate Agents and Managers
38 Cranbury Station Road, East Windsor, NJ 08512

Publications

Us Patents

Bipolar Transistor Structure With Self-Aligned Raised Extrinsic Base And Methods

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US Patent:
7037798, May 2, 2006
Filed:
Nov 12, 2004
Appl. No.:
10/904482
Inventors:
Thomas N. Adam - Poughkeepsie NY, US
Kevin K. Chan - Staten Island NY, US
Alvin J. Joseph - Williston VT, US
Marwan H. Khater - Poughkeepsie NY, US
Qizhi Liu - Essex Junction VT, US
Beth Ann Rainey - Williston VT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/331
US Classification:
438312, 438316, 438318, 438320, 438341, 438350, 438356, 438357, 438359
Abstract:
The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e. g. , high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

Bipolar Transistor Structure With Self-Aligned Raised Extrinsic Base And Methods

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US Patent:
7119416, Oct 10, 2006
Filed:
Jun 29, 2005
Appl. No.:
11/169444
Inventors:
Thomas N. Adam - Poughkeepsie NY, US
Kevin K. Chan - Staten Island NY, US
Alvin J. Joseph - Williston VT, US
Marwan H. Khater - Poughkeepsie NY, US
Qizhi Liu - Essex Junction VT, US
Beth Ann Rainey - Williston VT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27/82
H01L 29/70
US Classification:
257592, 257E21044
Abstract:
The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e. g. , high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

Methods Of Forming Structure And Spacer And Related Finfet

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US Patent:
20060154423, Jul 13, 2006
Filed:
Dec 19, 2002
Appl. No.:
10/538911
Inventors:
David Fried - Brewster NY, US
Edward Nowak - Junction VT, US
Beth Rainey - Williston VT, US
International Classification:
H01L 21/336
US Classification:
438283000, 438286000
Abstract:
Methods for forming a spacer () for a first structure (), such as a gate structure of a FinFET, and at most a portion of a second structure (), such as a fin, without detrimentally altering the second structure. The methods generate a first structure () having a top portion () that overhangs an electrically conductive lower portion () and a spacer () under the overhang (). The overhang () may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin () such as regions adjacent and under the gate structure (), and allows for exposing sidewalls of the fin () to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin () and construction of the gate structure () and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin () during spacer processing. A FinFET () including a gate structure () and spacer () is also disclosed.
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Beth A Rainey from Pottersville, NJ, age ~74 Get Report