Bernardo Z Rub

6404573, Jun 11, 2002

Sep 9, 1998

09/150259

Bernardo Rub - Edina MN
Hamid R. Shafiee - Bloomington MN

Seagate Technology LLC - Scotts Valley CA

G11B 509

360 46, 360 40, 360 48, 360 53, 341 59, 114792

A detector is provided to detect data values within a data signal that is sampled to provide temporally separated data samples. A first detector portion is configured to determine the location of a first sample vector in a first signal space. A second detector portion is configured to determine the location of a second sample vector in a second signal space. The second detector portion determines the location by using a logic statement to combine a plurality of location indicators. Each location indicator provides the location of the second sample vector relative to a respective boundary surface. The form of the logic statement is independent of the values of the location indicators. In addition, each location indicator is independent of all other location indicators.

6480125, Nov 12, 2002

May 31, 2001

09/871513

Bernardo Rub - Edina MN
Kinhing P. Tsang - Plymouth MN

Seagate Technology LLC - Scotts Valley CA

H03M 700

341 50, 341 59, 341 67

Methods of encoding and decoding as well as an encoder and decoder are provided for encoding data words into codewords and decoding codewords into data words. The data words are encoded by mapping each data word into a number of data segments. Each data segment is then encoded to form a codeword segment that has the same number of bits as the data word segment. The codeword segments are concatenated to form the codeword. The codewords are decoded by decoding individual codeword segments into data word segments that are the same size as the codeword segments. The data word segments are then mapped into the data word, which has fewer bits than the total number of bits across all data word segments.

6594096, Jul 15, 2003

Jun 28, 2001

09/894981

Kenneth R. Burns - Bloomington MN
Srinivas Maddali - Scotts Valley CA
Jimmie Ray Shaver - Yukon OK
Bernardo Rub - Sudbury MA
Peter I. Vasiliev - Cupertino CA
Wuping Chen - San Jose CA
Kavi Alptekin - Santa Cruz CA
Gary W. Reininga - Saratoga CA
Robert D. Cronch - Edmond OK
Clifton J. Williamson - Soquel CA

Seagate Technology LLC - Scotts Valley CA

G11B 509

360 46, 360 51

Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.

6804805, Oct 12, 2004

Jun 26, 2001

09/891688

Bernardo Rub - Edina MN

Seagate Technology LLC - Scotts Valley CA

H03M 1329

714752, 714769

An encoder and method of encoding data words are provided, which map a block of at least one of the data words into an error correction code (ECC) code word. The ECC code word is defined by a plurality of multiple-bit ECC symbols which are separated by boundaries. Bit patterns are constrained from occurring in the ECC code word based on a relative location of the bit patterns to the boundaries.

7900125, Mar 1, 2011

Nov 30, 2006

11/606416

Jingfeng Liu - Longmont CO, US
Bernardo Rub - Sudbury MA, US
Peihui Zheng - Medfield MA, US

Seagate Technology LLC - Scotts Valley CA

G06F 11/00

714799, 714760, 714797, 714776

One or more techniques provide majority detection in error recovery. Accordingly, a device retries reading an ECC codeword having one or more bits for a plurality of retries, and stores each retry. The device (“hard” majority detection) votes on a value of each bit of the codeword based on a majority of corresponding retry values in the plurality of corresponding retries. Also, the device (“soft” majority detection) may determine reliability information for a value of each bit of the codeword based on a reoccurrence ratio of corresponding retry values in the plurality of retries. The device may declare erasures based on the reliability information and a (dynamically adjusted) threshold of uncertainty, e. g. , where an “uncertain” bit based on the threshold or any symbol with an “uncertain” bit is declared as an erasure.

8130553, Mar 6, 2012

Dec 2, 2009

12/629481

Bruce D. Buch - Westborough MA, US
Ara Patapoutian - Hopkinton MA, US
Bengt A. Ulriksson - Milford MA, US
Bernardo Rub - Sudbury MA, US

Seagate Technology LLC - Cupertino CA

G11C 16/04
G11C 16/06

36518524, 36518503, 36518509

This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

8243511, Aug 14, 2012

Sep 27, 2010

12/891475

Ara Patapoutian - Hopkinton MA, US
Bernardo Rub - Sudbury MA, US
Bruce D. Buch - Westborough MA, US

Seagate Technology LLC - Scotts Valley CA

G11C 16/08
G11C 16/28

36518502, 36518503, 36518509, 3651852, 714773, 714763

A nominal reference read operation compares analog voltages of the memory cells to at least one nominal reference voltage. A shifted reference read operation compares the analog voltages of the memory cells to at least one shifted reference voltage that is shifted from the nominal reference voltage to compensate for an expected change in the analog voltages of the memory cells. Data stored in the memory cells is decoded by a first decoding process that uses the information from either the nominal reference read operation or the shifted reference read operation. The data stored in the memory cells is decoded by a second decoding process that uses the information from both the nominal reference read operation and the shifted reference read operation.

8327226, Dec 4, 2012

Feb 3, 2010

12/699505

Bernardo Rub - Sudbury MA, US

Seagate Technology LLC - Cupertino CA

G11C 29/00

714763

An apparatus includes a memory that is allocated to reported portions and overprovisioned portions. The apparatus includes an error correction circuit that communicates with the memory in error correction coded data that has a controllable ECC length. The ECC length is a function of a history of error reports. A memory allocation engine balances a size of the overprovisioned portions to maintain a size of the reported portions. The balancing is performed as a function of an average of ECC lengths in the ECC length table over a time interval in which a size of the memory decreases with accumulated erase cycles of the memory.