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Berke Cetinoneri

from Palo Alto, CA
Age ~40
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Also known as:
Cetinoneri Berke, Berke R
Related to:
C Berke
Connected to:
Aerial L Cetnar, 32Christopher J Cetnar, 51Joy H Cetnar, 60Cheryl A Cetnik, 68Paul A Ceto, 47Jan Ceton, 80Lee A Cetrano, 66Traci J Cetraro, 54Justin M Cetro, 41Eric A Cetron, 56

Berke Cetinoneri Phones & Addresses

  • Palo Alto, CA
  • Santa Clara, CA
  • Sunnyvale, CA
  • San Jose, CA
  • 4077 Porte De Palmas, San Diego, CA 92122 (858) 587-7058
  • Encinitas, CA
  • La Jolla, CA
  • 4077 Porte De Palmas UNIT 7, San Diego, CA 92122 (858) 587-7058

Work

Position: Professional/Technical

Resumes

Resumes

Berke Cetinoneri Photo 1

Senior Engineer, Rf Design

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Location:
3449 Mauricia Ave, Santa Clara, CA 95051
Industry:
Wireless
Work:
Apple
Senior Engineer, Rf Design
Qualcomm Jan 2011 - Feb 2015
Staff Engineer, Rfic Design
Education:
Uc San Diego 2006 - 2011
Doctorates, Doctor of Philosophy, Electrical Engineering Uc San Diego 2006 - 2008
Master of Science, Masters, Electrical Engineering Sabanci University 2002 - 2006
Bachelors, Bachelor of Science, Engineering
Skills:
Analog Circuit Design
Circuit Design
Mixed Signal
Rf
Ic
Analog
Antennas
Digital Signal Processors
Asic
Soc
Cadence Virtuoso
Cmos
Verilog
Signal Processing
Agilent Ads
Simulations
Matlab
Radio Frequency
Integrated Circuits
Languages:
English
Berke Cetinoneri Photo 2

Berke Cetinoneri

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Publications

Us Patents

Multiple-Input Multiple-Output (Mimo) Low Noise Amplifiers For Carrier Aggregation

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US Patent:
20130316670, Nov 28, 2013
Filed:
Aug 24, 2012
Appl. No.:
13/593764
Inventors:
Aleksandar Miodrag Tasic - San Diego CA, US
Anosh Bomi Davierwalla - San Diego CA, US
Berke Cetinoneri - Encinitas CA, US
Jusung Kim - San Diego CA, US
Chiewcharn Narathong - Laguna Niguel CA, US
Klaas van Zalinge - La Jolla CA, US
Gurkanwal Singh Sahota - San Diego CA, US
James Ian Jaffee - Solana Beach CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H03G 3/20
US Classification:
4552341
Abstract:
Multiple-input multiple-output (MIMO) low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a MIMO LNA having a plurality of gain circuits, a drive circuit, and a plurality of load circuits. The gain circuits receive at least one input radio frequency (RF) signal and provide at least one amplified RF signal. Each gain circuit receives and amplifies one input RF signal and provides one amplified RF signal when the gain circuit is enabled. The at least one input RF signal include transmissions sent on multiple carriers at different frequencies to the wireless device. The drive circuit receives the at least one amplified RF signal and provides at least one drive RF signal. The load circuits receive the at least one drive RF signal and provide at least one output RF signal.

Impedance Balancing For Transmitter To Receiver Rejection

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US Patent:
20130109330, May 2, 2013
Filed:
Oct 26, 2011
Appl. No.:
13/282354
Inventors:
Gurkanwal Singh Sahota - San Diego CA, US
Frederic Bossu - San Diego CA, US
Berke Cetinoneri - La Jolla CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
H04B 1/40
US Classification:
455 77
Abstract:
Exemplary embodiments are directed to impedance balancing within a transceiver. A device may include a transformer having a first side coupled to a transmit path and a second side coupled to a receive path. Further, the device may include an antenna tuning network coupled to a first portion of the first side and configured for coupling to an antenna. The device may also include an adjustment unit coupled to a second portion of the first side and configured for being adjusted to enable an impedance at the adjustment unit to be substantially equal to an impedance at the antenna tuning network.

Distributed-Element Filter For Mmwave Frequencies

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US Patent:
20230064458, Mar 2, 2023
Filed:
Aug 25, 2021
Appl. No.:
17/411892
Inventors:
- Cupertino CA, US
Bo Zhang - San Jose CA, US
Mingjuan Zhu - Saratoga CA, US
Chi V. Pham - San Jose CA, US
Berke Cetinoneri - Palo Alto CA, US
Timothy B. Ogilvie - San Jose CA, US
International Classification:
H04B 1/04
H04B 1/00
H04B 1/52
Abstract:
Frequency-filtering circuitry is disclosed that rejects power of a wireless signal having an undesired frequency while causing a decreased power loss to a wireless signal having a desired frequency using distributed elements, rather than lumped elements. The frequency-filtering circuitry may reject at least 5 decibels of power of a wireless signal having a frequency over 32 gigahertz, while causing a power loss of at most 1.1 decibels to a wireless signal having a frequency lower than 29.5 gigahertz. The frequency-filtering circuitry may include a main branch, a first parallel branch coupled and parallel to the main branch via a first connecting trace, and a second parallel branch coupled and parallel to the main branch via a second connecting trace. The first connecting trace intersects the main branch and the first parallel branch, and the second connecting trace intersects the main branch and the second parallel branch.

Electronic Devices Having Antenna Module Isolation Structures

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US Patent:
20200106185, Apr 2, 2020
Filed:
Sep 28, 2018
Appl. No.:
16/146488
Inventors:
- Cupertino CA, US
Qishan Yu - San Jose CA, US
Harish Rajagopalan - San Jose CA, US
Berke Cetinoneri - Santa Clara CA, US
International Classification:
H01Q 11/14
H01Q 1/42
H01Q 1/38
H01Q 3/44
Abstract:
An electronic device may be provided with a phased antenna array controlled by phase and magnitude controllers within an integrated circuit. The array may be formed on antenna layers and the integrated circuit may be mounted to transmission line layers of a dielectric substrate. A ground plane may separate the transmission line layers from the antenna layers. A connector may be mounted to the surface of the transmission line layers and may be coupled to the integrated circuit using conductive traces. A passive resonator may be formed in the antenna layers and may include conductive structures that resonate at one-quarter of the effective wavelength of operation of the array to form an open circuit impedance for surface currents generated on the ground plane by the array. This may serve to block the surface currents from scattering at an edge of the ground plane and leaking onto the integrated circuit.

Systems And Methods For Compression Distortion Compensation For Wireless Signals

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US Patent:
20200092153, Mar 19, 2020
Filed:
Sep 19, 2018
Appl. No.:
16/135973
Inventors:
- Cupertino CA, US
Berke Cetinoneri - Santa Clara CA, US
Qishan Yu - San Jose CA, US
International Classification:
H04L 27/26
H04B 7/155
H04B 17/318
H03G 3/30
Abstract:
Systems, methods, and devices are provided for correcting compression distortion of wireless signals due to variations in operation parameters of the radio frequency system. The method may include using circuitry to generate a reference signal that is not pre-distorted by a processing block. The method may involve receiving an envelope signal representative of a signal being transmitted by a transceiver. The method may also involve determining a first peak-to-average ratio of the envelope signal and receiving a second peak-to-average ratio of the reference signal. The method may additionally involve determining a difference between the first peak-to-average ratio and the second peak-to-average ratio. The method may also include adjusting a gain of an amplifier of the transceiver based on the difference.

Wireless Communications Systems With Envelope Tracking Capabilities

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US Patent:
20180368065, Dec 20, 2018
Filed:
Jun 16, 2017
Appl. No.:
15/625318
Inventors:
- Cupertino CA, US
Berke Cetinoneri - Santa Clara CA, US
Evan M. Manrique - Hayward CA, US
Ryan J. Goedken - Santa Clara CA, US
International Classification:
H04W 52/02
H04B 1/40
H03F 3/19
H03F 3/24
H03F 1/32
H03G 3/30
G01R 29/10
G01R 29/08
Abstract:
An electronic device may include wireless communications circuitry, control circuitry, and sensor circuitry. The wireless communications circuitry may include amplifier circuitry that amplifies radio-frequency signals using on a bias voltage to generate amplified radio-frequency signals transmitted over an antenna. Power supply circuitry may generate the bias voltage based on an envelope mapping setting and an envelope signal associated with the radio-frequency signals. The sensor circuitry may generate sensor data that characterizes the performance of the wireless communications circuitry and provide the sensor data to the control circuitry. The control circuitry may use the provided sensor data to generate control signals for the power supply circuitry. The control signals may adjust the envelope mapping setting of the power supply circuitry.
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Berke Cetinoneri from Palo Alto, CA, age ~40 Get Report