Resumes
Resumes
Beifang Qiu Phones & Addresses
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14633 Ambric Knolls Rd, Saratoga, CA 95070
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San Jose, CA
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Tracy, CA
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1126 Lexington Dr, Sunnyvale, CA 94087
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Nashville, TN
Work
Position:
Professional/Technical
Education
Degree:
Associate degree or higher
Publications
Us Patents
Method And Apparatus For Performing Rlc Modeling And Extraction For Three-Dimensional Integrated Circuit (3D-Ic) Designs
View pageUS Patent:
8146032, Mar 27, 2012
Filed:
Jan 30, 2009
Appl. No.:
12/363485
Inventors:
Qiushi Chen - San Jose CA, US
Beifang Qiu - Sunnyvale CA, US
Charles C. Chiang - Saratoga CA, US
Xiaoping Hu - Sunnyvale CA, US
Mathew Koshy - San Mateo CA, US
Baribrata Biswas - San Jose CA, US
Beifang Qiu - Sunnyvale CA, US
Charles C. Chiang - Saratoga CA, US
Xiaoping Hu - Sunnyvale CA, US
Mathew Koshy - San Mateo CA, US
Baribrata Biswas - San Jose CA, US
Assignee:
Synopsys, Inc. - Mountain View CA
International Classification:
G06F 17/50
G06F 9/455
G06F 9/455
US Classification:
716106, 716 51, 716101, 716107, 716111, 716132, 716136, 716137, 716138, 716139
Abstract:
One embodiment of the present invention provides a system that performs an RLC extraction for a three-dimensional integrated circuit (3D-IC) die. During operation, the system receives a 3D-IC die description. The system then transforms the 3D-IC die description into a set of 2D-IC die descriptions, wherein the transform maintains equivalency between the set of 2D-IC die descriptions and the 3D-IC die description. Next, for each 2D-IC die description in the set of 2D-IC die descriptions, the system performs an electrical property extraction using a 2D-IC extraction tool to obtain a 2D-IC RLC netlist file. The system then combines the set of 2D-IC RLC netlist files for the set of 2D-IC die descriptions to form an RLC netlist file for the 3D-IC die description.
Method And Apparatus For Facilitating Variation-Aware Parasitic Extraction
View pageUS Patent:
20070124707, May 31, 2007
Filed:
Nov 14, 2006
Appl. No.:
11/599145
Inventors:
Edhi Sutjahjo - Cupertino CA, US
Byungwook Kim - Los Altos Hills CA, US
Goetz Leonhardt - San Jose CA, US
Beifang Qiu - Sunnyvale CA, US
Sergey Krasnovsky - Portland OR, US
Baribrata Biswas - San Jose CA, US
Alex Gyure - San Jose CA, US
Mahmoud Shahram - Cupertino CA, US
Byungwook Kim - Los Altos Hills CA, US
Goetz Leonhardt - San Jose CA, US
Beifang Qiu - Sunnyvale CA, US
Sergey Krasnovsky - Portland OR, US
Baribrata Biswas - San Jose CA, US
Alex Gyure - San Jose CA, US
Mahmoud Shahram - Cupertino CA, US
International Classification:
G06F 17/50
US Classification:
716004000
Abstract:
One embodiment of the present invention provides a system for determining an electrical property for an interconnect layer. During operation, the system receives interconnect technology data which includes nominal parameter values for a first interconnect layer, and parameter-variation values which represent variations in the nominal parameter values due to random process variations. Next, the system receives an interconnect template which describes the geometry of a portion of a second interconnect layer. The system then determines electrical property data for the interconnect template using the interconnect technology data. The electrical property data can include a nominal electrical property value, and sensitivity values which represent the sensitivities of the nominal electrical property value to variations in the nominal parameter values. Next, the system stores the electrical property data and the interconnect technology data in a storage.
Determining Eco Aggressor Nets During Incremental Extraction
View pageUS Patent:
20160350470, Dec 1, 2016
Filed:
May 24, 2016
Appl. No.:
15/163628
Inventors:
- Mountain View CA, US
Arthur NIEUWOUDT - Mountain View CA, US
Mathieu DRUT - San Jose CA, US
Beifang QIU - Saratoga CA, US
Arthur NIEUWOUDT - Mountain View CA, US
Mathieu DRUT - San Jose CA, US
Beifang QIU - Saratoga CA, US
International Classification:
G06F 17/50
Abstract:
A computer-implemented method of extracting parasitics associated with a circuit design layout generated by modifying a previous iteration of the layout, includes, in part, identifying a first multitude of nets that have been changed in the circuit design layout relative to the previous iteration of the circuit design layout. The method further includes, in part, calculating a first multitude of parasitic capacitance values between each of the first multitude of first nets and each of a second multitude of nets disposed in proximity of the first multitude of nets. The method further includes, in part, identifying each net in the second multitude of nets as an aggressor net if a number defined by the net's associated parasitic capacitance value is higher than a threshold value. The method further includes excluding nets in the second multitude of second nets that are not identified as aggressor nets from the parasitic extraction.