Been Yih Jin

7470972, Dec 30, 2008

Mar 11, 2005

11/078267

Jack Kavalieros - Portland OR, US
Justin K. Brask - Portland OR, US
Mark L. Doczy - Beaverton OR, US
Matthew V. Metz - Hillsboro OR, US
Suman Datta - Beaverton OR, US
Brian S. Doyle - Portland OR, US
Robert S. Chau - Beaverton OR, US
Everett X. Wang - San Jose CA, US
Philippe Matagne - Beaverton OR, US
Lucian Shifren - Hillsboro OR, US
Been Y. Jin - Lake Oswego OR, US
Mark Stettler - Hillsboro OR, US
Martin D. Giles - Portland OR, US

Intel Corporation - Santa Clara CA

H01L 29/20

257615, 257 19, 257616, 257382, 257E29104, 257E29193, 438933, 438217, 438194

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form SiGe. The highest layer may be of the form SiGeon the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form SiGeon the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

8269209, Sep 18, 2012

Dec 18, 2009

12/653847

Uday Shah - Portland OR, US
Benjamin Chu-Kung - Hillsboro OR, US
Been Y. Jin - Lake Oswego OR, US
Ravi Pillarisetty - Portland OR, US
Marko Radosavljevic - Beaverton OR, US
Willy Rachmady - Beaverton OR, US

Intel Corporation - Santa Clara CA

H01L 29/06

257 9, 257E29168, 257E2109, 257 24, 257 19, 257E29072, 257E21403, 977762, 977938

The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

8283653, Oct 9, 2012

Dec 23, 2009

12/646477

Ravi Pillarisetty - Portland OR, US
Jack T. Kavalieros - Portland OR, US
Willy Rachmady - Beaverton OR, US
Uday Shah - Portland OR, US
Benjamin Chu-Kung - Hillsboro OR, US
Marko Radosavljevic - Beaverton OR, US
Niloy Mukherjee - Beaverton OR, US
Gilbert Dewey - Hillsboro OR, US
Been Y. Jin - Lake Oswego OR, US
Robert S. Chau - Beaverton OR, US

Intel Corporation - Santa Clara CA

H01L 29/06

257 20, 257 19, 257 18, 257 14, 257 15, 257E29005

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e. g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e. g. , SiGe or GaAs or AlGaAs), a doping layer (e. g. , delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

8575596, Nov 5, 2013

Oct 9, 2012

13/647952

Ravi Pillarisetty - Portland OR, US
Jack T. Kavalieros - Portland OR, US
Willy Rachmady - Beaverton OR, US
Uday Shah - Portland OR, US
Benjamin Chu-Kung - Hillsboro OR, US
Marko Radosavljevic - Beaverton OR, US
Niloy Mukherjee - Beaverton OR, US
Gilbert Dewey - Hillsboro OR, US
Been Y. Jin - Lake Oswego OR, US
Robert S. Chau - Beaverton OR, US

Intel Corporation - Santa Clara CA

H01L 31/00

257 24, 257E21409

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e. g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e. g. , SiGe or GaAs or AlGaAs), a doping layer (e. g. , delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

20090075445, Mar 19, 2009

Nov 19, 2008

12/313368

Jack Kavalieros - Portland OR, US
Justin K. Brask - Portland OR, US
Mark L. Doczy - Beaverton OR, US
Matthew V. Metz - Hillsboro OR, US
Suman Datta - Beaverton OR, US
Brian S. Doyle - Portland OR, US
Robert S. Chau - Beaverton OR, US
Everett X. Wang - San Jose CA, US
Philippe Matagne - Beaverton OR, US
Lucian Shifren - Hillsboro OR, US
Been Y. Jin - Lake Oswego OR, US
Mark Stettler - Hillsboro OR, US
Martin D. Giles - Portland OR, US

H01L 21/336

438300, 257E21431

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form SiGe. The highest layer may be of the form SiGeon the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form SiGeon the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

20180047839, Feb 15, 2018

Oct 23, 2017

15/790907

- Santa Clara CA, US
JACK T. KAVALIEROS - Portland OR, US
WILLY RACHMADY - Beaverton OR, US
UDAY SHAH - Portland OR, US
BENJAMIN CHU-KUNG - Hillsboro OR, US
MARKO RADOSAVLJEVIC - Portland OR, US
NILOY MUKHERJEE - Portland OR, US
GILBERT DEWEY - Beaverton OR, US
BEEN Y. JIN - Lake Oswego OR, US
ROBERT S. CHAU - Beaverton OR, US

INTEL CORPORATION - Santa Clara CA

H01L 29/775
B82Y 10/00
H01L 29/778
H01L 29/66
H01L 29/267
H01L 29/15
H01L 29/10
H01L 29/06
H01L 29/78
H01L 21/76
H01L 29/51
H01L 29/165

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

20160172472, Jun 16, 2016

Feb 15, 2016

15/043935

- Santa Clara CA, US
JACK T. KAVALIEROS - Portland OR, US
WILLY RACHMADY - Beaverton OR, US
UDAY SHAH - Portland OR, US
BENJAMIN CHU-KUNG - Hillsboro OR, US
MARKO RADOSAVLJEVIC - Portland OR, US
NILOY MUKHERJEE - Portland OR, US
GILBERT DEWEY - Beaverton OR, US
BEEN Y. JIN - Lake Oswego OR, US
ROBERT S. CHAU - Beaverton OR, US

INTEL CORPORATION - Santa Clara CA

H01L 29/775
H01L 29/06
H01L 29/78
H01L 29/15

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.

20140103397, Apr 17, 2014

Dec 27, 2013

14/141648

Ravi Pillarisetty - Portland OR, US
Jack T. Kavalieros - Portland OR, US
Willy Rachmady - Beaverton OR, US
Uday Shah - Portland OR, US
Benjamin Chu-Kung - Hillsboro OR, US
Marko Radosavljevic - Beaverton OR, US
Niloy Mukherjee - Beaverton OR, US
Gilbert Dewey - Hillsboro OR, US
Been Y. Jin - Lake Oswego OR, US
Robert S. Chau - Hillsboro OR, US

H01L 29/66
H01L 29/78

257192

Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V semiconductor materials and includes a germanium fin structure. In one example case, a non-planar quantum well device is provided, which includes a quantum well structure having a substrate (e.g. SiGe or GaAs buffer on silicon), a IV or III-V material barrier layer (e.g., SiGe or GaAs or AlGaAs), a doping layer (e.g., delta/modulation doped), and an undoped germanium quantum well layer. An undoped germanium fin structure is formed in the quantum well structure, and a top barrier layer deposited over the fin structure. A gate metal can be deposited across the fin structure. Drain/source regions can be formed at respective ends of the fin structure.