Search

Barry Wayne Sassman

from Leander, TX
Age ~52
Get Report
Also known as:
Barry W Sassman, Barry S Sassman
Related to:
Gilbert SassmannCamille L Sassman, 54Elizabeth Sassman, 75Gene SassmannGilbert Sassmann
Connected to:
Michael D Sassmann, 55Tod Sassman, 65Alice M Sasso, 67Brenda L Sasso, 83Chiara F Sasso, 46Colleen M Sasso, 66Ellen C Sasso, 71Geoffrey Sasso, 57Geraldine V Sasso, 94Grace M Sasso, 103

Barry Sassman Phones & Addresses

  • Leander, TX
  • 2225 Drue Ln, Cedar Park, TX 78613
  • 2201 Lakeline Blvd, Cedar Park, TX 78613
  • 2201 S Lakeline Blvd APT 3201, Cedar Park, TX 78613
  • 7920 San Felipe Blvd, Austin, TX 78729 (512) 401-0824
  • 1720 Wells Branch Pkwy, Austin, TX 78728 (512) 990-0698
  • Round Rock, TX
  • Universal City, TX

Work

Position: Professional/Technical

Education

Degree: Associate degree or higher

Resumes

Resumes

Barry Sassman Photo 1

Process Engineer Technician-Integration

View page
Location:
1424 Uhland Dr, Leander, TX
Industry:
Semiconductors
Work:
Spansion Jul 2014 - Nov 2014
Manufactring Engineer
Skorpios Technologies, Inc. Jul 2014 - Nov 2014
Process Engineer Technician-Integration
Tlmi Corp Apr 2013 - Jul 2014
Process Engineer
Sematech Dec 2002 - Mar 2013
Process Engineer
Amd 1990 - 1996
Process Engineer
Education:
Southwestern University 1990 - 1995
Bachelors, Bachelor of Arts, Chemistry
Skills:
Semiconductors
Semiconductor Industry
Process Engineering
Design of Experiments
Silicon
Thin Films
Metrology
Process Integration
Pvd
Failure Analysis
Spc
Cvd
Process Simulation
Plasma Etch
Jmp
Cmos
Lithography
Characterization
Manufacturing
Photolithography
Product Engineering
Etching
Semiconductor Device
Mems
Device Characterization
Ic
Barry Sassman Photo 2

Process Engineer At Sematech

View page
Position:
Process Engineer at Sematech
Location:
Austin, Texas Area
Industry:
Semiconductors
Work:
Sematech
Process Engineer
Education:
Southwestern University 1990 - 1995

Publications

Us Patents

Methods For Nanoscale Feature Imprint Molding

View page
US Patent:
20100081278, Apr 1, 2010
Filed:
Aug 28, 2006
Appl. No.:
11/467822
Inventors:
Muhammad Mustafa Hussain - Austin TX, US
Naim Moumen - Walden NY, US
Gabriel Gebara - Austin TX, US
Ed Labelle - Austin TX, US
Sidi Lanee - Austin TX, US
Barry Sassman - Cedar Park TX, US
Raj Jammy - Austin TX, US
International Classification:
H01L 21/768
H01L 21/30
US Classification:
438666, 438702, 257E21211, 257E21585
Abstract:
Methods for fabricating nanoscale features are disclosed. One technique involves depositing onto a substrate, where the first layer may be a silicon layer and may subsequently be etched. A second layer and third layer may be deposited on the etch first layer, followed by the deposition of a silicon cap. The second and third layer may be etched, exposing edges of the second and third layers. The cap and first layer may be removed and either the second or third layer may be etched, creating a nanoscale pattern.
Control profile
Barry Wayne Sassman from Leander, TX, age ~52 Get Report