Resumes
Resumes
Asit Mallick Phones & Addresses
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Saratoga, CA
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Santa Clara, CA
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12067 Ingrid Ct, Saratoga, CA 95070
Publications
Us Patents
Method For Efficiently Identifying Errant Processes In A Computer System By The Operating System (Os) For Error Containment And Error Recovery
View pageUS Patent:
7131029, Oct 31, 2006
Filed:
Mar 16, 2004
Appl. No.:
10/801153
Inventors:
Nhon T. Quach - Santa Clara CA, US
Amy L. O'Donnell - Chandler AZ, US
Asit K. Mallick - Santa Clara CA, US
Koichi Yamada - Los Gatos CA, US
Amy L. O'Donnell - Chandler AZ, US
Asit K. Mallick - Santa Clara CA, US
Koichi Yamada - Los Gatos CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 11/00
G06F 12/00
G06F 12/00
US Classification:
714 15, 714 20, 714 34, 712244, 711203
Abstract:
The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error. In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in a processor including at least one critical memory structure to detect an error and a processor error processing logic hardware coupled to the at least one critical memory structure. The processor error processing logic hardware to store a physical address of an errant process that caused the error, store an execution instruction pointer (IP) in an interruption instruction pointer (IIP), determine a first virtual address from an operating system mapping table, determine a second virtual address from a translation look-aside buffer, and identify the errant process, if the physical address and the second virtual address match the physical address and the first virtual address.
Method And Apparatus For Managing Virtual Addresses
View pageUS Patent:
7383374, Jun 3, 2008
Filed:
Mar 31, 2005
Appl. No.:
11/096175
Inventors:
Koichi Yamada - Los Gatos CA, US
Felix Leung - San Jose CA, US
Amy Santoni - Austin TX, US
Asit Mallick - Santa Clara CA, US
Rohit Seth - Santa Clara CA, US
Gary Hammond - Fort Collins CO, US
Felix Leung - San Jose CA, US
Amy Santoni - Austin TX, US
Asit Mallick - Santa Clara CA, US
Rohit Seth - Santa Clara CA, US
Gary Hammond - Fort Collins CO, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711 6, 711207
Abstract:
A method for managing virtual memory addresses includes associating a guest identifier (ID) with a virtual machine accessing a virtual memory address. A physical memory address is retrieved corresponding to the virtual memory address utilizing the guest ID. Other embodiments are described and claimed.
Enabling Multiple Instruction Stream/Multiple Data Stream Extensions On Microprocessors
View pageUS Patent:
7768518, Aug 3, 2010
Filed:
Sep 27, 2006
Appl. No.:
11/528121
Inventors:
Jamison Collins - San Jose CA, US
Perry Wang - San Jose CA, US
Bernard Lint - Mountain View CA, US
Koichi Yamada - Los Gatos CA, US
Asit Mallick - Santa Clara CA, US
Richard A. Hankins - San Jose CA, US
Gautham Chinya - Hillsboro OR, US
Perry Wang - San Jose CA, US
Bernard Lint - Mountain View CA, US
Koichi Yamada - Los Gatos CA, US
Asit Mallick - Santa Clara CA, US
Richard A. Hankins - San Jose CA, US
Gautham Chinya - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15/80
US Classification:
345505, 345506, 345686, 345 11, 345522, 345520
Abstract:
Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. In one embodiment, a lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing.
Mechanism To Schedule Threads On Os-Sequestered Sequencers Without Operating System Intervention
View pageUS Patent:
8607235, Dec 10, 2013
Filed:
Dec 30, 2004
Appl. No.:
11/027445
Inventors:
Richard A. Hankins - San Jose CA, US
Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Trung A. Diep - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Asit K. Mallick - Santa Clara CA, US
Baiju V. Patel - Portland OR, US
James Paul Held - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Prashant Sethi - Folsom CA, US
Xinmin Tian - San Jose CA, US
Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Trung A. Diep - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant E. Bigbee - Scottsdale AZ, US
John P. Shen - San Jose CA, US
Asit K. Mallick - Santa Clara CA, US
Baiju V. Patel - Portland OR, US
James Paul Held - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Prashant Sethi - Folsom CA, US
Xinmin Tian - San Jose CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
Method, apparatus and system embodiments to schedule OS-independent “shreds” without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
Managing And Implementing Metadata In Central Processing Unit Using Register Extensions
View pageUS Patent:
8635415, Jan 21, 2014
Filed:
Sep 30, 2009
Appl. No.:
12/571269
Inventors:
Baiju V. Patel - Portland OR, US
Rajeev Gopalakrishna - Hillsboro OR, US
Andrew F. Glew - Hillsboro OR, US
Robert J. Kushlis - Worcester MA, US
Don Alan Van Dyke - Rescue CA, US
Joseph Frank Cihula - Hillsboro OR, US
Asit K. Mallick - Saratoga CA, US
James B. Crossland - Banks OR, US
Gilbert Neiger - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Martin Guy Dixon - Portland OR, US
Mark Jay Charney - Lexington MA, US
Jacob (Koby) Gottlieb - Kiryat Tivon, IL
Rajeev Gopalakrishna - Hillsboro OR, US
Andrew F. Glew - Hillsboro OR, US
Robert J. Kushlis - Worcester MA, US
Don Alan Van Dyke - Rescue CA, US
Joseph Frank Cihula - Hillsboro OR, US
Asit K. Mallick - Saratoga CA, US
James B. Crossland - Banks OR, US
Gilbert Neiger - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Martin Guy Dixon - Portland OR, US
Mark Jay Charney - Lexington MA, US
Jacob (Koby) Gottlieb - Kiryat Tivon, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/02
G06F 9/302
G06F 9/302
US Classification:
711154, 711201, 711E12002, 712221, 712225, 712 E9017
Abstract:
A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.
Method For Efficiently Identifying Errant Processes In A Computer System By The Operating System (Os) For Error Containment And Error Recovery
View pageUS Patent:
20020188895, Dec 12, 2002
Filed:
Dec 8, 2000
Appl. No.:
09/732306
Inventors:
Nhon Quach - Santa Clara CA, US
Amy O'Donnell - Chandler AZ, US
Asit Mallick - Santa Clara CA, US
Koichi Yamada - Los Gatos CA, US
Amy O'Donnell - Chandler AZ, US
Asit Mallick - Santa Clara CA, US
Koichi Yamada - Los Gatos CA, US
International Classification:
G06F011/00
US Classification:
714/048000
Abstract:
The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP). The method further includes determining a first virtual address from an operating system mapping table, determining a second virtual address from a translation look-aside buffer, and identifying the errant process, if the physical address and the second virtual address match the physical address and the first virtual address.
Transferring Registers In Transitions Between Computer Environments
View pageUS Patent:
20070136724, Jun 14, 2007
Filed:
Dec 12, 2005
Appl. No.:
11/301934
Inventors:
Arun Sharma - Union City CA, US
Rohit Seth - Santa Clara CA, US
Asit Mallick - Santa Clara CA, US
Rohit Seth - Santa Clara CA, US
Asit Mallick - Santa Clara CA, US
International Classification:
G06F 9/455
US Classification:
718001000
Abstract:
A method and apparatus for transferring registers in transitions between computer environments. An embodiment of a method includes running a first process in a first computer environment and switching to a second process in a second computer environment. The method further provides for transferring a register to the second computer environment. A process for transferring the register is based at least in part on current states of the first computer environment and the second computer environment.
Methods And Apparatuses For Reducing Power Consumption Of Processor Switch Operations
View pageUS Patent:
20090089562, Apr 2, 2009
Filed:
Sep 27, 2007
Appl. No.:
11/904395
Inventors:
Ethan Schuchman - Santa Clara CA, US
Hong Wang - Fremont CA, US
Chris Weaver - Austin TX, US
Belliappa M. Kuttanna - Austin TX, US
Asit Mallick - Santa Clara CA, US
Vivek K. De - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
Hong Wang - Fremont CA, US
Chris Weaver - Austin TX, US
Belliappa M. Kuttanna - Austin TX, US
Asit Mallick - Santa Clara CA, US
Vivek K. De - Beaverton OR, US
Per Hammarlund - Hillsboro OR, US
International Classification:
G06F 9/312
US Classification:
712228, 712E09033
Abstract:
Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.