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Aryesh Amar

from Austin, TX
Age ~58
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Also known as:
Aryeshneelu J Amar, Amitesh Amar, Achalesh Amar
Phone and address:
10312 Dalea Vista Ct, Austin, TX 78739
Related to:
Elaine Amar
Connected to:
Anne L Amar, 68Barak Amar, 55Dalia K Amar, 54Danit L Amar, 48David Amar, 71Elmahdi M Amar, 50Erin E Amar, 57Fatima M Amar, 53Felix Amar, 76Frederic A Amar, 60

Aryesh Amar Phones & Addresses

  • 10312 Dalea Vista Ct, Austin, TX 78739
  • 6 Autumn Leaf Dr, Nashua, NH 03060 (603) 891-4960
  • 23 Congress St, Nashua, NH 03062 (603) 881-9897
  • Pullman, WA
  • 1129 Elder Cir, Austin, TX 78733

Industries

Semiconductors

Resumes

Resumes

Aryesh Amar Photo 1

Aryesh Amar

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Location:
Austin, TX
Industry:
Semiconductors

Business Records

Name / Title
Company / Classification
Phones & Addresses
Aryesh Amar
Officer
CLEANTECH INTEGRATED CIRCUITS LLC
Mfg Electronic Components
5104 Jekins Cv, Austin, TX 78730
6606 Mapleshade Ln, Dallas, TX 75252
10312 Dalea Vis Ct, Austin, TX 78739
Aryesh Amar
Managing
ARNAVI, LLC
Nonclassifiable Establishments
10312 Dalea Vis Ct, Austin, TX 78739

Publications

Us Patents

Independent Control Of Calibration Registers In A Multi Channel A-D Converter

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US Patent:
6426713, Jul 30, 2002
Filed:
Oct 25, 2000
Appl. No.:
09/695708
Inventors:
Aryesh Amar - Nashua NH
Edwin De Angel - Austin TX
Eric J. Swanson - Buda TX
Assignee:
Cirrus Logic, Inc. - Austin
International Classification:
H03M 106
US Classification:
341118, 341120, 341144
Abstract:
In a signal processing integrated circuit having a plurality of physical channels and a plurality of gain registers, a plurality of offset registers and an plurality of setup registers, mechanisms are provided to assign one of a plurality of gain registers independently of a selected one of a plurality of offset registers when processing signals from a physical channel.

Method And System For Selecting Implementation Of A Filter Controller Between A Single Conversion Mode That Ensures A Fully-Settled Converted Output And A Continuous Conversion Mode

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US Patent:
6469650, Oct 22, 2002
Filed:
Mar 6, 2001
Appl. No.:
09/800604
Inventors:
Kartik Nanda - Nashua NH
Aryesh Amar - Nashua NH
Saibun Wong - Nashua NH
Jerome E. Johnston - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 112
US Classification:
341155, 341118, 341120, 341143, 341157
Abstract:
A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

Use Of Pointers To Enhance Flexibility Of Serial Port Interface For An Integrated Circuit With Programmable Components

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US Patent:
6522274, Feb 18, 2003
Filed:
May 28, 1999
Appl. No.:
09/321583
Inventors:
Aryesh Amar - Nashua NH
Jerome E. Johnston - Austin TX
Donald Keith Coffey - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 112
US Classification:
341141, 341155, 341139
Abstract:
A method and apparatus are used to process a plurality of analog signals on a corresponding plurality of physical channels using a circuit having analog to digital converter (ADC) components, a serial port interface, and a serial port controller. Logical channel information for one or more logical channels is stored in a register on the serial port controller. Each logical channel specifies one of the physical channels and conversion information. Command bits are set over a serial port input pin, and include at least one pointer bit indicative of a selected logical channel. In response to the command bits, the serial port controller sends signals indicative of the physical channel and the converter property specified in the selected logical channel to the ADC components.

Application Of A Conditionally Stable Instrumentation Amplifier To Industrial Measurement

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US Patent:
6525589, Feb 25, 2003
Filed:
Oct 25, 2000
Appl. No.:
09/695705
Inventors:
Axel Thomsen - Austin TX
Edwin De Angel - Austin TX
Sherry Wu - Austin TX
Aryesh Amar - Nashua NH
Jerome E. Johnston - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03K 1716
US Classification:
327379, 327336
Abstract:
An instrumentation circuit has an integrated circuit that has input terminals, an amplifier arrangement using feed forward compensation and an analog to digital converter and a serial data output receiving the output from said amplifier arrangement. A bridge circuit, having a transducer, or a thermocouple arrangement are connected to input terminals of the integrated circuit.

Method And System For Powering Down An Analog-To-Digital Converter Into A Sleep Mode

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US Patent:
6642879, Nov 4, 2003
Filed:
Jul 16, 2001
Appl. No.:
09/906916
Inventors:
Aryesh Amar - Nashua NH
Philip Steiner - Nashua NH
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H03M 112
US Classification:
341155, 713324
Abstract:
A method and system for powering down an analog-to-digital converter (âADCâ) into a sleep mode are disclosed. If the ADC receives a normal set of pulses for a serial clock signal of the ADC, a serial interface controller outputs converted data requested by a user through a serial interface. Also, if the ADC receives a sleep set of pulses for the serial clock signal, a state machine of the ADC powers down the ADC into a sleep mode in which at least parts of the ADC are operated at a reduced power consumption level. Furthermore, if the ADC is in the sleep mode and the ADC receives a wake-up set of pulses for the serial clock signal, the state machine powers back up the ADC from the sleep mode.

Integrated Circuit With A Mode Control Selecting Settled And Unsettled Output From A Filter

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US Patent:
6857002, Feb 15, 2005
Filed:
Oct 25, 2000
Appl. No.:
09/695704
Inventors:
Axel Thomsen - Austin TX, US
Jerome E. Johnston - Austin TX, US
Edwin De Angel - Austin TX, US
Aryesh Amar - Nashua NH, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G06F017/10
G06F013/00
US Classification:
708300, 708168, 708305
Abstract:
In a signal processing integrated circuit having an analog to digital converter and a digital filter having a plurality of taps separated in time, when starting a conversion after a reset or a change of input channel, the filter will have an incomplete set of input data as the delayed inputs to an output calculation are all zero from the reset operation. After reset, during the time that data are filling up the filter pipeline, the calculation of an output value will give a result that holds information about the input, but does not present the data with the same scaling and frequency content as the fully settled filter. The integrated circuit selectively provides two modes, on that provides only fully settled data from the filter or and another that provides all data from the filter, including unsettled data. Knowledge about the filter coefficients can be utilized by a user or user process to extract information about the input from the unsettled data.

Techniques For Signal Measurement Using A Conditionally Stable Amplifier

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US Patent:
6891430, May 10, 2005
Filed:
Oct 25, 2000
Appl. No.:
09/695706
Inventors:
Axel Thomsen - Austin TX, US
Edwin De Angel - Austin TX, US
Sherry Wu - Austin TX, US
Lei Wang - Chelmsford MA, US
Aryesh Amar - Nashua NH, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
G06G007/12
US Classification:
327560, 327 74
Abstract:
A signal processing integrated circuit has having a chopper stabilized, multistage, feedforward amplifier and a delta sigma analog to digital converter. Filtering of the output of the output from the analog to digital converter comprises a sincfilter and a sincfilter. The sincfilter may be bypassed. A rough buffer permits quick charging of a sample and hold capacitor during part of the charge cycle and slower but more accurate charging during the remainder of the charge cycle.

Single Clock Data Communication In Direct Stream Digital System

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US Patent:
6956919, Oct 18, 2005
Filed:
Nov 12, 2002
Appl. No.:
10/292320
Inventors:
Aryesh Amar - Austin TX, US
Brian David Trotter - Austin TX, US
Jason Powell Rhode - Austin TX, US
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H04L007/00
US Classification:
375355, 375316
Abstract:
Methods and apparatus are provided for receiving DSD data in phase modulation mode using a single clock signal. Either the bit clock or phase signal may be used.
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Aryesh Amar from Austin, TX, age ~58 Get Report