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Anwar Q Rohillah

from Dublin, CA
Age ~50
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Also known as:
Anwar Quinones Rohillah, Andwar Q Rohillah, Rohillah Anwar
Related to:
Katrina D Rohillah
Connected to:
Anita Rohilla, 46Ashish Rohilla, 40Mina R Rohin, 37Robert Rohinsky, 61Eli S Rohl, 49Joe Rohl, 66Karl B Rohl, 67Stephanie K Rohl, 54Tony L Rohl, 70Tonya M Rohl, 52

Anwar Rohillah Phones & Addresses

  • Dublin, CA
  • Sunnyvale, CA
  • Santa Clara, CA
  • San Diego, CA
  • Austin, TX
  • Hillsboro, OR
  • La Jolla, CA

Work

Company: Qualcomm May 2012 Address: San Diego, CA Position: Computer architect

Education

School / High School: University of Waterloo 1991 to 1996 Specialities: Computer Engineering

Skills

Computer Architecture • Microarchitecture • Simulations • Soc • C • C++ • Processors • Microprocessors

Languages

English

Industries

Semiconductors

Resumes

Resumes

Anwar Rohillah Photo 1

Computer Architect

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Location:
7057 Kalmia Hl Ct, Dublin, CA
Industry:
Semiconductors
Work:
Qualcomm - San Diego, CA since May 2012
Computer Architect
Intel - Austin, TX Aug 2004 - Apr 2012
Computer Architect
Intel - HIllsboro, OR Sep 2000 - Aug 2004
Computer Architect
Intel - Austin, TX May 1999 - Aug 2000
Computer Architect
Ross Technology - Austin, TX Jun 1996 - Aug 1998
Circuit Design Engineer, Performance Architect
Education:
University of Waterloo 1991 - 1996
Skills:
Computer Architecture
Microarchitecture
Simulations
Soc
C
C++
Processors
Microprocessors
Languages:
English

Publications

Us Patents

System And Method For Using A Mask Register To Track Progress Of Gathering Elements From Memory

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US Patent:
7984273, Jul 19, 2011
Filed:
Dec 31, 2007
Appl. No.:
11/967482
Inventors:
Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US
Tom Forsyth - Kirkland WA, US
Michael Abrash - Kirkland WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/312
US Classification:
712225, 712 4, 712 6
Abstract:
A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

Mechanism For Effectively Caching Streaming And Non-Streaming Data Patterns

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US Patent:
8065488, Nov 22, 2011
Filed:
Oct 20, 2010
Appl. No.:
12/908183
Inventors:
Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/12
US Classification:
711134, 711136, 711E1207, 711E12071
Abstract:
A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

Mechanism For Effectively Caching Streaming And Non-Streaming Data Patterns

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US Patent:
8108614, Jan 31, 2012
Filed:
Dec 31, 2007
Appl. No.:
11/967413
Inventors:
Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - Palo Alto CA, US
International Classification:
G06F 12/12
US Classification:
711134, 711136, 711E1207, 711E12071
Abstract:
A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data.

Device, System, And Method For Improving Processing Efficiency By Collectively Applying Operations

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US Patent:
20090171994, Jul 2, 2009
Filed:
Dec 31, 2007
Appl. No.:
11/967492
Inventors:
Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US
Tom Forsyth - Kirkland WA, US
Michael Abrash - West Kirkland WA, US
International Classification:
G06F 17/30
US Classification:
707101, 707E17009
Abstract:
A system and method for generating a single compressed vector including two or more predetermined attribute values. For each of a plurality of data points such as pixels, if a first and a second attribute values of the data point are equal to a first and a second, respectively, of the two or more predetermined attribute values, the compressed vector is used to operate on the data point. Other embodiments are described and claimed.

Methods, Apparatus, And Instructions For Converting Vector Data

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US Patent:
20090172349, Jul 2, 2009
Filed:
Dec 26, 2007
Appl. No.:
11/964631
Inventors:
Eric Sprangle - Austin TX, US
Robert D. Cavin - Sunnyvale CA, US
Anwar Rohillah - Austin TX, US
Douglas M. Carmean - Beaverton OR, US
International Classification:
G06F 9/30
US Classification:
712 4, 712E09021
Abstract:
A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

Device, System, And Method For Using A Mask Register To Track Progress Of Gathering Elements From Memory

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US Patent:
20110264863, Oct 27, 2011
Filed:
Jul 5, 2011
Appl. No.:
13/175953
Inventors:
Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco TX, US
Tom Forsyth - Kirkland WA, US
Michael Abrash - Kirkland WA, US
International Classification:
G06F 12/08
G06F 9/30
US Classification:
711125, 711E12017, 712E09028
Abstract:
A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

Methods, Apparatus, And Instructions For Converting Vector Data

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US Patent:
20130232318, Sep 5, 2013
Filed:
Mar 15, 2013
Appl. No.:
13/844111
Inventors:
Eric Sprangle - Austin TX, US
Robert D. Cavin - Sunnyvale CA, US
Anwar Rohillah - San Diego CA, US
Douglas M. Carmean - Beaverton OR, US
International Classification:
G06F 9/30
US Classification:
712 4
Abstract:
A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

Methods, Apparatus, And Instructions For Converting Vector Data

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US Patent:
20140019720, Jan 16, 2014
Filed:
Feb 7, 2013
Appl. No.:
13/762220
Inventors:
Eric Sprangle - Austin TX, US
Robert D. Cavin - Sunnyvale CA, US
Anwar Rohillah - Austin TX, US
Douglas M. Carmean - Beaverton OR, US
International Classification:
G06F 9/30
US Classification:
712206
Abstract:
A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.
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Anwar Q Rohillah from Dublin, CA, age ~50 Get Report