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Andrew E Horch

from Seattle, WA
Age ~59
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Also known as:
Andrew Edward Horch, Andy Horch
Phone and address:
3626 Wallingford Ave, Seattle, WA 98103
(206) 547-0165
Related to:
Kelly J Horch, 59Abigail Horch, 24Daniel J Horch, 54Nancy S Horch, 88Ana Horch, 46
Connected to:
Joseph A Horch, 50Lola Horch, 87Robert C Horch, 103Tiffany D Horch, 34Lori A Horcha, 65Gayle A Horchler, 80Matthew T Horchler, 55Roger Horchow, 96William Horchuck, 63Shawn Horcoff, 46

Andrew Horch Phones & Addresses

  • 3626 Wallingford Ave, Seattle, WA 98103 (206) 547-0165
  • 3843 Ashworth Ave N, Seattle, WA 98103 (206) 547-0165
  • 2801 Western Ave, Seattle, WA 98121 (206) 443-6946
  • 1180 Reed Ave, Sunnyvale, CA 94086
  • 13841 Pioneer Rd, Portland, OR 97229 (503) 350-2354
  • 1600 Villa St, Mountain View, CA 94041
  • Worcester, MA
  • New York, NY
  • Boise, ID
  • Hillsboro, OR
  • 3626 Wallingford Ave N APT 3C, Seattle, WA 98103 (206) 547-0165

Work

Position: Clerical/White Collar

Emails

a***[email protected]

Industries

Semiconductors

Resumes

Resumes

Andrew Horch Photo 1

Andrew Horch

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Location:
Greater Seattle Area
Industry:
Semiconductors

Publications

Us Patents

Thyristor-Based Device Having Extended Capacitive Coupling

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US Patent:
6583452, Jun 24, 2003
Filed:
Dec 17, 2001
Appl. No.:
10/023060
Inventors:
Hyun-Jin Cho - Palo Alto CA
Andrew Horch - Sunnyvale CA
Scott Robins - San Jose CA
Farid Nemati - Menlo Park CA
Assignee:
T-RAM, Inc. - Mountain View CA
International Classification:
H01L 2974
US Classification:
257107, 257133, 257147
Abstract:
A thyristor-based semiconductor device has a thyristor that exhibits increased capacitive coupling between a conductive structure and a portion of a thyristor. According to an example embodiment of the present invention, the thyristor-based semiconductor device is manufactured having an extended portion that is outside a current path through the thyristor and that capacitively couples a conductive structure to a portion of the thyristor for controlling the current through the path. In one particular implementation, the extended portion extends from a base region of the thyristor and is outside of a current path through the base region and between an adjacent base region and an adjacent emitter region. A gate is formed capacitively coupled to the base region via the extended portion. In this manner, the control of the thyristor with the gate exhibits increased capacitive coupling, as compared to the control without the extended portion.

Non-Volatile Memory Element Having A Cascoded Transistor Scheme To Reduce Oxide Field Stress

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US Patent:
6636442, Oct 21, 2003
Filed:
Jan 29, 2002
Appl. No.:
10/059624
Inventors:
Michael Rowlandson - Portland OR
Andrew Horch - Sunnyvale CA
Assignee:
Lattice Semiconductor Corporation - Hillsboro CA
International Classification:
G11C 1604
US Classification:
36518528, 36518505, 36518502
Abstract:
A non-volatile memory cell (FIG. ) is provided which includes three transistors, a floating gate non-volatile storage transistor ( ) and two cascode connected select transistors ( ). The two cascoded select transistors ( ) act together to block the programming voltage when the memory cell is included in an array, and the memory cell is not selected for programming. A value of an unselect voltage applied to the gate of the first cascode connected transistor ( ) is set to prevent breakdown of the oxide in the first cascode transistor ( ) as well as the second cascode transistor ( ). A value of an unselect voltage applied to the gate of the second cascode connected transistor ( ) can be selected so that the voltage passed to the floating gate storage transistor ( ) will not result in a program drain disturb, or source disturb condition.

Thyristor-Based Device Over Substrate Surface

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US Patent:
6653174, Nov 25, 2003
Filed:
Dec 17, 2001
Appl. No.:
10/023052
Inventors:
Hyun-Jin Cho - Palo Alto CA
Andrew Horch - Mountain View CA
Scott Robins - San Jose CA
Farid Nemati - Menlo Park CA
Assignee:
T-RAM, Inc. - San Jose CA
International Classification:
H01L 21332
US Classification:
438133, 438135, 257133
Abstract:
A semiconductor device having a thyristor is manufactured in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor. A control port is formed capacitively coupled to at least one of the base regions.

Shunt Connection To Emitter

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US Patent:
6666481, Dec 23, 2003
Filed:
Oct 1, 2002
Appl. No.:
10/262728
Inventors:
Andrew Horch - Sunnyvale CA
Scott Robins - San Jose CA
Assignee:
T-Ram, Inc. - San Jose CA
International Classification:
H01L 29423
US Classification:
287133, 257137, 257146, 257163
Abstract:
A semiconductor device is formed having a thyristor, a pass device and a conductive shunt that electrically connects an emitter region of the thyristor with a node near an upper surface of the substrate. In one example embodiment of the present invention, the conductive shunt is formed in a trench in a substrate and extending from an upper surface of the substrate to an emitter region of a vertical thyristor, with the emitter region being in the substrate and below the upper surface. In one implementation, the thyristor includes a thyristor body and a control port, with an N+ emitter region of the thyristor body being in the substrate and below and upper surface thereof. A pass device is formed adjacent to the thyristor, and the conductive shunt is formed in a trench extending from the N+ emitter region to a source/drain region of the pass device. With this approach, thyristor applications can be implemented having an emitter region in a substrate and not necessarily directly accessible, for example, via an upper surface of the substrate. This approach is also useful, for example, in applications where a cathode-down thyristor is used, such as when it is desirable to form the thyristor control port near a bottom portion of the thyristor, and in high-density circuit applications, such as memory arrays.

Recessed Thyristor Control Port

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US Patent:
6683330, Jan 27, 2004
Filed:
Oct 1, 2002
Appl. No.:
10/262697
Inventors:
Andrew Horch - Sunnyvale CA
Scott Robins - San Jose CA
Assignee:
T-Ram, Inc. - San Jose CA
International Classification:
H01L 2974
US Classification:
257133, 257146, 257163, 257170
Abstract:
A semiconductor device is formed including a substrate having an upper surface, a thyristor region in the substrate and a control port adapted for capacitively coupling to at least a portion of the thyristor region via a dielectric material. According to an example embodiment of the present invention, a trench is formed in the substrate and subsequently filled with materials including dielectric material and a control port. The control port is adapted for capacitively coupling to the thyristor via the dielectric material for controlling current flow in the thyristor (e. g. , for causing an outflow of minority carriers from a portion of the thyristor for switching the thyristor from conducting state to a blocking state). A portion of the substrate adjacent to the upper surface is implanted with a species of ions, and the dielectric material via which the control port capacitively couples to the thyristor does not include the species of ions. In one implementation, a filled portion of the trench over the control port inhibits ions from implanting the dielectric material.

Thyristor-Based Device Adapted To Inhibit Parasitic Current

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US Patent:
6686612, Feb 3, 2004
Filed:
Oct 1, 2002
Appl. No.:
10/263382
Inventors:
Andrew Horch - Sunnyvale CA
Scott Robins - San Jose CA
Assignee:
T-Ram, Inc. - San Jose CA
International Classification:
H01L 29423
US Classification:
257133, 257146
Abstract:
Parasitic current leakage from a thyristor-based semiconductor device is inhibited. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor body portion and a control port located in a substrate, the control port being adapted for capacitively coupling to the thyristor body portion for controlling current flow therein. The substrate further includes a doped circuit region separated by a channel region from another doped region of similar polarity in the substrate. The control port faces the channel region in the substrate, and the channel region is susceptible to current leakage in response to voltage pulses being applied to the control port for controlling current flow in the thyristor. The device is arranged such that such current leakage in the channel is inhibited while pulses are applied to the control port for controlling current flow in the thyristor; the parasitic current leakage between the doped circuit region and the doped region in the substrate is inhibited.

Thyristor-Based Device Over Substrate Surface

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US Patent:
6690038, Feb 10, 2004
Filed:
Jul 23, 2002
Appl. No.:
10/200987
Inventors:
Hyun-Jin Cho - Palo Alto CA
Andrew Horch - Mountain View CA
Scott Robins - San Jose CA
Farid Nemati - Menlo Park CA
Assignee:
T-Ram, Inc. - San Jose CA
International Classification:
H01L 29423
US Classification:
257133, 257147, 257155, 365180
Abstract:
A semiconductor device having a thyristor is arranged in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices, as well as facilitates the implementation of the semiconductor device in a variety of applications. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor. A control port is formed capacitively coupled to at least one of the base regions.

Thyristor-Based Device That Inhibits Undesirable Conductive Channel Formation

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US Patent:
6690039, Feb 10, 2004
Filed:
Oct 1, 2002
Appl. No.:
10/262787
Inventors:
Farid Nemati - Menlo Park CA
Andrew Horch - Sunnyvale CA
Scott Robins - San Jose CA
Assignee:
T-Ram, Inc. - San Jose CA
International Classification:
H01L 29423
US Classification:
257133, 257138, 257153
Abstract:
A semiconductor device is adapted to inhibit the formation of a parasitic MOS-inversion channel between an emitter region and a gated base in a capacitively-coupled thyristor device. According to an example embodiment of the present invention, a thyristor having first and second base regions coupled between emitter regions is gated, via one of the base regions, to a control port. The control port exhibits a workfunction between the control port and the base region that inhibits the formation of a conductive channel between the base region and an adjacent emitter region, such as when the semiconductor device is in a standby and/or a read mode for memory implementations. The workfunction is selected such that the parasitic MOS-inversion channel would turn on is sufficiently high to enable the operation of the device at voltages that are optimized for a particular implementation while remaining below V. With this approach, the thyristor can be operated without necessarily turning âonâ the parasitic MOS-inversion channel.
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Andrew E Horch from Seattle, WA, age ~59 Get Report