Search

Anand Govind

from Fremont, CA
Age ~52
Get Report
Also known as:
Aman Govind, Anand Gorind, B Govind
Phone and address:
398 Apache Ct, Fremont, CA 94539
(510) 687-0175
Related to:
Shobana Rajan, 54Jaganathan Govind, 86Shobhana Rajan, 44Jaganathan GovindSaumya Rajan, 48Vijayalaks Rajan, 73Vijayalakshmi Rajan, 72
Connected to:
Arjun B Govindan, 31Arun A Govindaraju, 46Arvind K Govindarajulu, 44Bhuvaneswari Govindarajan, 48Brittney Govind, 36Chandan Govindarajulu, 52Deepika Govindan, 43Ganesh Govindan, 52Gopal G Govindasamy, 69Govind A Govind, 31

Anand Govind Phones & Addresses

  • 398 Apache Ct, Fremont, CA 94539 (510) 687-0175 (510) 687-1002
  • 398 Apache Ct #13, Fremont, CA 94539 (510) 687-1002
  • 119 Wenatchee Cmn, Fremont, CA 94539 (510) 687-0175
  • 287 Woodcreek Cmn, Fremont, CA 94539 (510) 656-9074
  • Los Altos, CA
  • College Park, MD
  • Beltsville, MD
  • San Jose, CA
  • Alameda, CA
  • Charlotte, NC

Work

Company: O9 solutions, inc. Sep 2019 Position: Senior vice president and gm, high technician industries

Education

Degree: Master of Business Administration, Masters School / High School: University of California, Berkeley

Skills

Financial Modeling • Valuation • Corporate Finance • Mergers and Acquisitions • Management • Strategic Planning • Business Strategy • Executive Relationships • Executive Level Relationship Building • Investment Banking • Investor Positioning • Capital Markets • Cross Functional Team Leadership • Business Development • Due Diligence • Leadership • Capital Raising • Financial Analysis • Investor Relations • Growth Strategies • Financial Planning and Analysis • Negotiations • Deal Structuring

Industries

Computer Software

Resumes

Resumes

Anand Govind Photo 1

Senior Vice President And Gm, High Technician Industries

View page
Location:
San Francisco, CA
Industry:
Computer Software
Work:
O9 Solutions, Inc.
Senior Vice President and Gm, High Technician Industries
Morgan Stanley Apr 2017 - Aug 2019
Managing Director
J.p. Morgan Jul 2007 - Apr 2017
Executive Director
Lsi Corporation Feb 1997 - Jul 2007
Senior Manager
Uc Berkeley Haas School of Management 2006 - 2007
Mba Student
Education:
University of California, Berkeley
Master of Business Administration, Masters Indian Institute of Technology, Madras
University of Maryland
Master of Science, Masters, Mechanical Engineering
Skills:
Financial Modeling
Valuation
Corporate Finance
Mergers and Acquisitions
Management
Strategic Planning
Business Strategy
Executive Relationships
Executive Level Relationship Building
Investment Banking
Investor Positioning
Capital Markets
Cross Functional Team Leadership
Business Development
Due Diligence
Leadership
Capital Raising
Financial Analysis
Investor Relations
Growth Strategies
Financial Planning and Analysis
Negotiations
Deal Structuring

Publications

Us Patents

Microstrip Package Having Optimized Signal Line Impedance Control

View page
US Patent:
6531932, Mar 11, 2003
Filed:
Jun 27, 2001
Appl. No.:
09/894210
Inventors:
Anand Govind - Fremont CA
Farshad Ghahghahi - Los Gatos CA
Aritharan Thurairajaratnam - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01P 308
US Classification:
333 34, 333238
Abstract:
A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.

Integrated Circuit Test Vehicle

View page
US Patent:
6534968, Mar 18, 2003
Filed:
Aug 10, 2001
Appl. No.:
09/928071
Inventors:
Leah M. Miller - Fremont CA
Anand Govind - Fremont CA
Zafer Kutlu - Menlo Park CA
Chao-Wen Chung - Union City CA
Aritharan Thurairajaratnam - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01R 3100
US Classification:
3241581, 324500, 324537
Abstract:
An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.

Flip-Chip Ball Grid Array Package For Electromigration Testing

View page
US Patent:
6700207, Mar 2, 2004
Filed:
Aug 5, 2002
Appl. No.:
10/212448
Inventors:
Senol Pekin - San Jose CA
Anand Govind - San Jose CA
Carl Iwashita - San Carlos CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2348
US Classification:
257778, 257738, 438108, 174260
Abstract:
A test package for electromigration testing includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.

Method For Reliability Testing Leakage Characteristics In An Electronic Circuit And A Testing Device For Accomplishing The Source

View page
US Patent:
6701270, Mar 2, 2004
Filed:
Sep 20, 2001
Appl. No.:
09/957410
Inventors:
Leah M. Miller - Fremont CA
Anand Govind - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F 1900
US Classification:
702117, 714724, 324500
Abstract:
The present invention provides a method for reliability testing leakage characteristics in an electronic circuit, and a testing device for accomplishing the same. In an advantageous embodiment, the method includes dividing conductors of an electronic circuit into at least first and second noninterleaved regions having at least two conductors each. The method further includes forming conductor nets by electrically connecting ones of the at least two conductors of the first region to ones of the at least two conductors of the second region then testing for electrical leakage in the conductor nets.

Characteristic Impedance Equalizer And An Integrated Circuit Package Employing The Same

View page
US Patent:
6759921, Jul 6, 2004
Filed:
Aug 17, 2001
Appl. No.:
09/932716
Inventors:
Anand Govind - Fremont CA
Yogendra Ranade - Fremont CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H03H 738
US Classification:
333 34, 333246, 257692
Abstract:
The present invention provides a characteristic impedance equalizer and method of manufacture thereof for use with an integrated circuit package having first and second signal transmission zones. In one embodiment, the characteristic impedancs equalizer includes a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone. The characteristic impedance equalizer also includes a second conductor, coupled to the first conductor, having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.

Stiffener Design

View page
US Patent:
6825066, Nov 30, 2004
Filed:
Dec 3, 2002
Appl. No.:
10/308310
Inventors:
Yogendra Ranade - Fremont CA
Anand Govind - Fremont CA
Kumar Nagarajan - San Jose CA
Farshad Ghahghahi - Los Gatos CA
Aritharan Thurairajaratnam - San Jose CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 2144
US Classification:
438121, 438125, 438106, 438107, 438613, 438108, 257706, 257701, 257702, 257704
Abstract:
A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses. Because the major interior apertures does not need to be large enough to fit both the monolithic integrated circuit and the secondary circuit structure, there is more stiffener material available to provide structural support than there would be if the major interior aperture was large enough to fit both the monolithic integrated circuit and the secondary circuit structure.

Measurement Of Package Interconnect Impedance Using Tester And Supporting Tester

View page
US Patent:
6946866, Sep 20, 2005
Filed:
Jul 15, 2003
Appl. No.:
10/620057
Inventors:
Aritharan Thurairajaratnam - San Jose CA, US
Mohan Nagar - Cupertino CA, US
Anand Govind - Fremont CA, US
Farshad Ghahghahi - Los Gatos CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G01R031/02
G01R031/11
US Classification:
324765, 324534, 324754, 324761, 324763
Abstract:
A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i. e. , package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.

Substrate Via Layout To Improve Bias Humidity Testing Reliability

View page
US Patent:
7081672, Jul 25, 2006
Filed:
Mar 7, 2005
Appl. No.:
11/073802
Inventors:
Anand Govind - Fremont CA, US
Aritharan Thurairajaratnam - San Jose CA, US
Farshad Ghahghahi - Los Gatos CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 23/34
US Classification:
257724, 174262, 174263, 174264, 174265, 174266, 361780, 361767, 361768
Abstract:
A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
Control profile
Anand Govind from Fremont, CA, age ~52 Get Report