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Amaresh V Malipatil

from San Jose, CA
Age ~45
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Connected to:
Opas Malipun, 49Bashkim B Maliqi, 43Susan G Malis, 56Teresa Malisch, 59Joseph Malise, 65Diana M Malish, 78Wendi S Malishan, 30Richard P Maliska, 55Chastidy M Maliskey, 49Jason A Maliski, 49

Amaresh Malipatil Phones & Addresses

  • 2415 Stearman Ct UNIT 3, San Jose, CA 95132
  • Milpitas, CA
  • Notre Dame, IN
  • 1403 Foothill Meadows Ct, San Jose, CA 95131

Resumes

Resumes

Amaresh Malipatil Photo 1

Senior .Engineer

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Location:
San Jose, CA
Industry:
Mining & Metals
Work:
Bhushan Steel & Strips Ltd.
Senior .Engineer
M/S. Surana Industries Limited Aug 1, 2008 - Jun 1, 2013
Engineer
Education:
Poojya Doddappa Appa College of Engg 2004 - 2008
Bachelor of Engineering, Bachelors, Mechanical Engineering
Skills:
Project Engineering
Engineering
Commissioning
Metallurgy
Maintenance and Repair
Procurement
Project Planning
Interests:
Education
Environment
Poverty Alleviation
Human Rights
Animal Welfare
Health
Amaresh Malipatil Photo 2

Amaresh Malipatil

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Location:
San Jose, CA
Industry:
Semiconductors
Skills:
Signal Processing
Matlab
Ofdm
Digital Signal Processors
Wireless
C
System Architecture
C++
Serdes
Debugging
Wlan
Asic
Bluetooth
Dsp
Simulink
Sensors
Wireless Communications Systems
Clocking
Semiconductors
Simulations
Wireless Technologies
Application Specific Integrated Circuits
Algorithms

Publications

Us Patents

System For An Adaptive Floating Tap Decision Feedback Equalizer

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US Patent:
8121183, Feb 21, 2012
Filed:
Jul 13, 2007
Appl. No.:
11/777337
Inventors:
Lizhi Zhong - Sunnyvale CA, US
Ye Liu - San Jose CA, US
Catherine Yuk-fun Chow - San Jose CA, US
Ryan Jungsuk Park - San Jose CA, US
Freeman V. Zhong - San Ramon CA, US
Amaresh V. Malipatil - Milpitas CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03K 5/159
US Classification:
375230, 375233, 375229, 375234
Abstract:
A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric.

Methods And Apparatus For Decision-Feedback Equalization With Oversampled Phase Detector

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US Patent:
8379711, Feb 19, 2013
Filed:
Jun 30, 2009
Appl. No.:
12/495547
Inventors:
Pervez M. Aziz - Dallas TX, US
Adam B. Healey - Newburyport MA, US
Amaresh Malipatil - Milpitas CA, US
Lizhi Zhong - Sunnyvale CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
H03H 7/30
US Classification:
375233, 375350, 375355
Abstract:
Methods and apparatus are provided for decision-feedback equalization with an oversampled phase detector. A method is provided for detecting data in a receiver employing decision-feedback equalization. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and DFE transition data. One or more coefficients used for the DFE correction for the transition sample signals are adapted using the DFE transition data.

Tx Back Channel Adaptation Algorithm

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US Patent:
8472513, Jun 25, 2013
Filed:
Jan 14, 2009
Appl. No.:
12/353860
Inventors:
Amaresh Malipatil - Milpitas CA, US
Lizhi Zhong - Sunnyvale CA, US
Wenyi Jin - Sunnyvale CA, US
Ye Liu - San Jose CA, US
Assignee:
LSI Corporation - San Jose CA
International Classification:
H04B 3/46
US Classification:
375233, 375219, 375229
Abstract:
Disclosed is a method and system that adapts coefficients of taps of a Finite Impulse Response (FIR) filter to increase elimination of Inter-Symbol Interference (ISI) introduced into a digital communications signal due to distortion characteristics caused by a real-world communications channel. In the communications system there is a Finite Impulse Response (FIR) filter. The FIR filter has at least one pre and/or post cursor tap that removes pre and/or post cursor ISI from the signal, respectively. The pre/post cursor taps each have pre/post cursor coefficients, respectively, that adjusts the effect of the pre/post cursor portion of the FIR filter. The FIR filtered signal is transmitted over the channel which distorts the signal due to the changing and/or static distortion characteristics of the channel. The channel distorted signal is received at a receiver that may pass the channel distorted signal through a quantifier/decision system (e. g. , a slicer) as the quantifier input signal to quantify the quantifier input signal to one of multiple digital values.

Low-Power Down-Sampled Floating Tap Decision Feedback Equalization

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US Patent:
8537885, Sep 17, 2013
Filed:
Mar 2, 2012
Appl. No.:
13/410735
Inventors:
Pervez Aziz - Dallas TX, US
Hiroshi Kimura - San Jose CA, US
Amaresh Malipatil - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03H 7/30
US Classification:
375233, 375226, 375229, 375230, 375232, 375234, 375316, 375346, 375350, 455 631, 455 6713, 4551142, 455296, 455501, 370335, 370342, 333 18, 333 28 R, 708300, 327551
Abstract:
In described embodiments, a variety of down-sampling techniques are employed to generate a more constrained set of floating-tap positions when compared to floating-tap Decision Feedback Equalization (DFE) architectures that allow unconstrained 1T resolution or separated floating-tap positions. Down-sampling is employed to constrain the floating-tap positions rather than positions occurring with 1T resolution or spacing. Two broad down-sampling techniques, phase pruning and phase amalgamation, are applied to a variety of exemplary DFE implementations. Although the tap positions are more constrained, the architectures select floating-tap positions containing dominant reflection inter-symbol interference (ISI) terms.

Pattern Detector For Serializer-Deserializer Adaptation

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US Patent:
8548038, Oct 1, 2013
Filed:
Dec 6, 2011
Appl. No.:
13/312443
Inventors:
Vladimir Sindalovsky - Perkasie PA, US
Mohammad S. Mobin - Orefield PA, US
Lane A. Smith - Easton PA, US
Amaresh V. Malipatil - San Jose CA, US
Pervez M. Aziz - Dallas TX, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03H 7/40
US Classification:
375232, 375350, 708323
Abstract:
In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Receiver Training With Cycle Slip Detection And Correction

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US Patent:
8605847, Dec 10, 2013
Filed:
Mar 9, 2011
Appl. No.:
13/043908
Inventors:
Mohammad Mobin - Orefield PA, US
Mark Trafford - Fleetwood PA, US
Ye Liu - San Jose CA, US
Vladimir Sindalovsky - Perkasie PA, US
Amaresh Malipatil - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04L 7/00
US Classification:
375355, 375229, 375232, 375233, 375316, 375354, 375358, 375371, 375373, 375376, 455260, 455502, 455516, 370503, 370508, 370509, 370510, 370511, 370512, 370513, 370514, 370516, 327141, 327147, 327156, 327163, 333 18, 333 28 R
Abstract:
In described embodiments, a transceiver includes a clock and data recovery module (CDR) with an eye monitor and a cycle slip monitor. The cycle slip detector monitors a CDR lock condition, which might be through detection of slips in sampling and/or transition timing detection. The cycle slip detector provides a check point to sense system divergence, allowing for a mechanism to recover CDR lock. In addition, when the CDR is out-of-lock, the various parameters that are adaptively set (e. g. , equalizer parameters) might be invalid during system divergence. Consequently, these parameters might be declared invalid by the system and not used.

Adjusting Sampling Phase In A Baud-Rate Cdr Using Timing Skew

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US Patent:
8649476, Feb 11, 2014
Filed:
Apr 7, 2011
Appl. No.:
13/081651
Inventors:
Amaresh Malipatil - San Jose CA, US
Ye Liu - San Jose CA, US
Freeman Y. Zhong - San Ramon CA, US
Chintan Desai - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04B 1/38
US Classification:
375355, 375219, 375229, 375233
Abstract:
In described embodiments, a transceiver includes a baud-rate clock and data recovery (CDR) module with an eye sampler, and an adaptation module for adaptively setting parameters of various circuit elements, such as timing, equalizer and gain elements. Data sampling clock phase of the CDR module is set for sampling at, for example, near the center of a data eye detected by the eye sampler, and the phase of data error sampling latch(es) is skewed by the CDR module with respect to the phase of the data sampling latch. Since the error signal driving the timing adaptation contains the information of the pulse response that the CDR module encounters, the phase of timing error sampling latch(es) of the CDR module is skewed based on maintaining a relative equivalence of input pulse response residual pre-cursor and residual post-cursor with respect to the timing error sampling clock phase.

Adaptation Of A Linear Equalizer Using A Virtual Decision Feedback Equalizer (Vdfe)

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US Patent:
20100046598, Feb 25, 2010
Filed:
Aug 19, 2008
Appl. No.:
12/193802
Inventors:
LIZHI ZHONG - Sunnyvale CA, US
Cathy Ye Liu - San Jose CA, US
Amaresh Virupanagouda Malipatil - Milpitas CA, US
Freeman Zhong - San Ramon CA, US
International Classification:
H03H 7/30
H03K 5/159
H03H 7/40
US Classification:
375233
Abstract:
A method and system of adaptation of a linear equalizer using a virtual decision feedback equalizer (VDFE) are disclosed. In one embodiment, a method of adjusting a setting of a linear equalizer includes determining a change to a decision feedback equalizer (DFE) tap weight value of a predefined metric according to a data signal and an error signal (e.g., the change may be generated according to an average of a specified plurality of data signals and the error signal); using the change in the DFE tap weight value to algorithmically generate a modification in a linear equalizer setting; and adjusting the linear equalizer setting. The linear equalizer is located in a feed-forward path and/or a feedback path of data transmission. The linear equalizer may be located in a transmitter and/or a receiver. The linear equalizer may be a continuous time linear equalizer and/or a Finite Impulse Response (FIR) linear equalizer.
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Amaresh V Malipatil from San Jose, CA, age ~45 Get Report