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Alok N Mehrotra

from Beaverton, OR
Age ~60
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Also known as:
Alok Melrotra, Alon Mehrota, Mehrotra Alok, Alon Z
Related to:
Stefani S Beach, 51Radha Rani Mehrotra, 47Mellika Beach, 32Urmila MehrotaA R MehotraPrem MehrotaRadha R Mehrotra, 49Radha R Dey, 47
Connected to:
Ajay P Mehrotra, 65Dinkar Mehrotra, 50Gaurav Mehrotra, 51Gita R Mehrotra, 51Khushboo Mehrotra, 40Madhumita Mehrotra, 64Rashmi Mehrotra, 73Shreyash Mehrotra, 50Sonal Mehrotra, 45Tejas Mehrotra, 36

Alok Mehrotra Phones & Addresses

  • Beaverton, OR
  • San Jose, CA
  • Campbell, CA
  • Naperville, IL
  • 16510 Los Gatos Almaden Rd, Los Gatos, CA 95032 (408) 358-8638

Resumes

Resumes

Alok Mehrotra Photo 1

Corporate Consultant And Certified Coach

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Location:
16510 Los Gatos Almaden Rd, Los Gatos, CA 95032
Industry:
Semiconductors
Work:
Magma Design Automation - Bangalore, India Mar 2010 - Apr 2012
VP, Sales and Managing Director
Synfora Jan 2009 - Mar 2010
Director of Sales
Sagantec Jun 2006 - May 2009
VP, WW Sales
SDS May 2005 - May 2006
VP, WW Sales
Magma Aug 2001 - May 2005
Director of Sales, Asia-Pac
Education:
Santa Clara University 1992 - 1996
MBA, Marketing State University of New York at Stony Brook 1988 - 1990
M.S., Computer Engineering Manipal Academy of Higher Education 1983 - 1988
B.E., Electronics & Telecommunications Springdales
Skills:
Product Marketing
Eda
Start Ups
Semiconductors
Asic
Product Management
Soc
Management
Ic
Embedded Systems
Go To Market Strategy
Leadership
Integration
Professional Services
Saas
Wireless
Creative Strategy
Sales
Entrepreneurship
Strategic Partnerships
Cross Functional Team Leadership
Enterprise Software
Business Strategy
Sales Management
Interests:
Social Services
Children
Civil Rights and Social Action
Education
Environment
Science and Technology
Human Rights
Languages:
English
Hindi
Alok Mehrotra Photo 2

Alok Mehrotra

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Industry:
Glass, Ceramics, & Concrete
Alok Mehrotra Photo 3

Alok Mehrotra

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Publications

Us Patents

Circuit For Testing Pumped Voltage Gates In A Programmable Gate Array

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US Patent:
59202017, Jul 6, 1999
Filed:
Sep 23, 1997
Appl. No.:
8/935567
Inventors:
Alok Mehrotra - Los Gatos CA
Charles R. Erickson - Fremont CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 2722
US Classification:
324765
Abstract:
In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V. sub. GG level, where V. sub. GG. gtoreq. V. sub. DD +V. sub. TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V. sub. GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Logic Gate Having Transmission Gate For Electrically Configurable Device Multiplexer

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US Patent:
57195072, Feb 17, 1998
Filed:
Feb 24, 1997
Appl. No.:
8/803686
Inventors:
Alok Mehrotra - Los Gatos CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 190948
US Classification:
326113
Abstract:
A 4. times. 1 multiplexer for an electrically configurable device uses novel logic gates to logically combine outputs from two SRAM memory cells to control pass gates between the multiplexer signal inputs and a multiplexer output. Each logic gate has three transistors. A complementary NMOS/PMOS pair of transistors defines a transmission gate. The gate of the NMOS transistor defines a first logic-gate input, while the gate of the PMOS transistor defines a second logic-gate input. Their sources are coupled and cooperatively define a third logic-gate input. Their drains are coupled and cooperatively define the logic-gate output. A third transistor, with its gate tied to the third input, couples the logic-gate output to ground when the transmission gate is OFF. The first and second logic-gate inputs are respectively coupled to complementary outputs of one memory cell, while the third logic gate input is coupled to an output of the other memory cell. The memory cells are "pumped" so that their output voltages are at least an NMOS transistor threshold voltage above the maximum signal level at the multiplexer signal inputs.

Circuit For Testing Pumped Voltage Gates In A Programmable Gate Array

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US Patent:
57173400, Feb 10, 1998
Filed:
Jan 17, 1996
Appl. No.:
8/588160
Inventors:
Alok Mehrotra - Los Gatos CA
Charles R. Erickson - Fremont CA
Assignee:
Xilink, Inc. - San Jose CA
International Classification:
G01R 2722
US Classification:
324765
Abstract:
In a field programmable gate array, a test circuit for testing the signal path of a line, through a pass gate, and onto a second line. A memory cell outputs at a V. sub. GG level, where V. sub. GG. gtoreq. V. sub. DD +V. sub. TN. In order to dynamically test the signal path, three transistors and two test signals are used to apply either 0 volts or V. sub. GG to control the pass gate. Two of the transistors are coupled to the memory cell and the pass gate, whereas the third transistor is coupled to the first and second transistors and ground. The two test signals and an inverter control these transistors so that the memory state can be changed to dynamically switch the pass gate according to the test configuration. An electrical signal is then sent through the signal path under test, and the result is monitored.

Programmable Single Buffered Six Pass Transistor Configuration

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US Patent:
56002645, Feb 4, 1997
Filed:
Oct 16, 1995
Appl. No.:
8/543454
Inventors:
Khue Duong - San Jose CA
Stephen M. Trimberger - San Jose CA
Alok Mehrotra - Los Gatos CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 1901
US Classification:
326 39
Abstract:
A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can also be programmably interconnected so that two signal channels are formed. The present invention modifies the known six transistor switch box so that one line output from the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors switch box is significantly reduced. For short line lengths, the buffer delay can be greater than the delay associated with the resistance and capacitance of the transistors of the switch box. In these cases, the output is not buffered and the buffer is programmably bypassed. Although there are four possible outputs that can be programmably selected in the present invention switch box, the present invention advantageously utilizes a single buffer resource to perform output buffering.
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Alok N Mehrotra from Beaverton, OR, age ~60 Get Report