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Allan D Knies

from Burlingame, CA
Age ~58
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Also known as:
Allan Douglas Knies, Allen D Knies
Phone and address:
155 Glen Aulin Ln, Burlingame, CA 94010
(650) 393-5114
Related to:
Chris Knies, 53Earl KniesElizabeth Knies, 86
Connected to:
Brandon L Knies, 42Julia E Knies, 101Justin Knies, 32Katherine Knies, 36Megan H Knies, 50John S Kniess, 67Donald R Kniesteadt, 81Johan W Kniestedt, 66Priscilla Knieste, 63Dale T Knievel, 80

Allan Knies Phones & Addresses

  • 155 Glen Aulin Ln, Burlingame, CA 94010 (650) 393-5114
  • 725 Cowper St, Palo Alto, CA 94301 (650) 473-3937
  • 312 Arkansas St, San Francisco, CA 94107
  • 522 Los Palmos Dr, San Francisco, CA 94127
  • Athens, OH
  • Sunnyvale, CA
  • West Lafayette, IN
  • San Mateo, CA

Professional Records

License Records

Allan R Knies Jr

License #:
20CC02689300 - Expired
Category:
Accountancy
Issued Date:
Jan 21, 1999
Expiration Date:
Dec 31, 2005
Type:
Certified Public Accountant

Resumes

Resumes

Allan Knies Photo 1

Performance And Simulation Lead

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Location:
155 Glen Aulin Ln, Burlingame, CA 94010
Industry:
Computer Software
Work:
Google
Performance and Simulation Lead
Intel Corporation Jul 2012 - Jul 2014
Processor Architecture R and D For Exascale Systems Pathfinding
Intel Corporation Sep 2009 - Jul 2012
Principal Engineer and Computer Architect
Intel Corporation Jan 2008 - Sep 2009
Director, Universal Parallel Computing Research Program
Intel Corporation May 2006 - Sep 2009
Associate Director
Education:
Purdue University 1988 - 1995
Doctorates, Doctor of Philosophy, Computer Engineering Ohio University Heritage College of Osteopathic Medicine 1984 - 1988
Bachelors, Bachelor of Science, Mathematics, Computer Science
Skills:
Computer Architecture
High Performance Computing
Parallel Computing
Microprocessors
Processors
Microarchitecture
Simulations
Compilers
Research
Multi Core
Performance Analysis
Languages:
English
Allan Knies Photo 2

Allan Knies

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Location:
Burlingame, CA
Industry:
Building Materials
Work:
Italcementi Group Mar 2008 - May 2017
Corporate Controller - Construction Materials
Mondi Group Jul 2005 - Aug 2007
Finance Director - Germany
Heidelbergcement Oct 2004 - Aug 2005
Assistant Controller - Northern Divsion
Heidelbergcement Aug 2001 - Sep 2004
Corporate Controller - Africa and Turkey
Heidelbergcement Mar 1998 - Aug 2001
Senior Internal Auditor - North America
Skills:
Business Process Improvement
Budgeting
Business Integration
Financial Analysis
Management Presentatons
Budgets
Financial Reporting
Internal Controls
Manufacturing
Sap
Process Improvement
Forecasting
Cost Accounting
Allan Knies Photo 3

Allan Knies

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Publications

Us Patents

Superword Memory-Access Instructions For Data Processor

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US Patent:
7680990, Mar 16, 2010
Filed:
May 30, 2003
Appl. No.:
10/449442
Inventors:
Donald C. Soltis - Fort Collins CO, US
Dale C. Morris - Steamboat Springs CO, US
Dean Ahmad Mulla - Saratoga CA, US
Achmed Rumi Zahir - Menlo Park CA, US
Amy Lynn O'Donnell - Ann Arbor MI, US
Allan Douglas Knies - San Francisco CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 12/00
G06F 13/00
G06F 13/28
US Classification:
711154
Abstract:
Atomic sixteen-byte memory accesses are provided in a 64-bit system in which eight of the bytes are stored in a 64-bit general-purpose register and eight of the bytes are stored in a 64-bit special-purpose register. A 16-byte load instruction transfers the low eight bytes to an explicitly specified general-purpose register, while the high eight bytes are transferred to the special-purpose register. Likewise, a 16-byte store instruction transfers data from a general-purpose register and the special-purpose register. Also provided is an 8-byte compare conditioning a 16-byte exchange semaphore instruction that can be used to accelerate algorithms that use multiple processors to simultaneously read and update large databases.

Mechanism To Increase Performance Of Control Speculation

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US Patent:
20040123081, Jun 24, 2004
Filed:
Dec 20, 2002
Appl. No.:
10/327556
Inventors:
Allan Knies - San Francisco CA, US
Kevin Rudd - Portland OR, US
Achmed Zahir - Menlo Park CA, US
Dale Morris - Steamboat Springs CO, US
Jonathan Ross - Woodinville WA, US
International Classification:
G06F009/44
US Classification:
712/225000
Abstract:
A mechanism for increasing the performance of control speculation comprises executing a speculative load, returning a data value to a register targeted by the speculative load if it hits in a cache, and associating a deferral token with the speculative load if it misses in the cache. The mechanism may also issue a prefetch on a cache miss to speed execution of recovery code if the speculative load is subsequently determined to be on the control flow path.

Scalable Cluster Router

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US Patent:
20110016223, Jan 20, 2011
Filed:
Jul 19, 2010
Appl. No.:
12/838785
Inventors:
Gianluca Iannaccone - Berkeley CA, US
Sylvia Ratnasamy - Berkeley CA, US
Maziar Manesh - Kensington CA, US
Katerina Argyraki - Lausanne, CH
Kevin Fall - Berkeley CA, US
Allan Knies - San Francisco CA, US
Norbert Egi - Somberek, HU
Mihai Dobrescu - Lausanne, CH
Salman Baset - New York NY, US
International Classification:
G06F 15/16
US Classification:
709232
Abstract:
Generally, this disclosure describes a scalable cluster router that includes a plurality of server-class computers interconnected together to form a router. Each server may be configured to independently schedule switching of packets to reduce the switch speed requirements on a per server basis. Each server may include a scheduler that independently load balances packet flows across servers of the cluster. Router capacity may be incrementally scaled by adding more servers, and router capacity may be increased by load balancing techniques within individual servers.

Methods And Apparatus To Provide Failure Detection

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US Patent:
20140006870, Jan 2, 2014
Filed:
Jun 29, 2012
Appl. No.:
13/538596
Inventors:
Joshua Bruce Fryman - Corvallis OR, US
Allan D. Knies - Burlingame CA, US
International Classification:
G06F 11/07
US Classification:
714 37
Abstract:
Methods and apparatus to provide failure detection are disclosed herein. An example method includes executing, via a plurality of computing nodes, first fenced computing operations; storing a count of issued data operations resulting from the first fenced computing operations; and determining whether a failure condition exists in the plurality of computing nodes by comparing the count of issued data operations to the count of performed data operations resulting from the first fenced computing operations.

System And Method For Adding An Instruction To An Instruction Set Architecture

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US Patent:
7143270, Nov 28, 2006
Filed:
Jan 30, 2004
Appl. No.:
10/769203
Inventors:
Kevin W. Rudd - Portland OR, US
Allan D. Knies - San Francisco CA, US
Dale C. Morris - Steamboat Springs CO, US
James M. Hull - Saratoga CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 9/44
US Classification:
712227
Abstract:
A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause the first register to be set to a first value using the feature indicator and to cause the second register to be set to a second value using the feature indicator. The execution core is configured to execute the first sequence of one or more instructions to cause a function to be performed in response to the first value in the first register indicating a true condition, and the execution core is configured to execute a second sequence of one or more instructions to cause the function to be performed in response to the second value in the second register indicating the true condition.

Way Partitioning For A System-Level Cache

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US Patent:
20210255972, Aug 19, 2021
Filed:
Dec 31, 2020
Appl. No.:
17/139750
Inventors:
- Mountain View CA, US
Xiaoyu Ma - Mountain View CA, US
Hongil Yoon - San Jose CA, US
Keith Robert Pflederer - Mountain View CA, US
Weiping Liao - Fremont CA, US
Benjamin Dodge - San Jose CA, US
Albert Meixner - Mountain View CA, US
Allan Douglas Knies - Burlingame CA, US
Manu Gulati - Saratoga CA, US
Rahul Jagdish Thakur - Santa Clara CA, US
Jason Rupert Redgrave - Mountain View CA, US
International Classification:
G06F 13/16
G06F 12/0811
G06F 12/0877
G06F 12/0815
Abstract:
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

System-Level Cache

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US Patent:
20200257639, Aug 13, 2020
Filed:
Jul 22, 2019
Appl. No.:
16/518503
Inventors:
- Mountain View CA, US
Xiaoyu Ma - Mountain View CA, US
Hongil Yoon - San Jose CA, US
Keith Robert Pflederer - Mountain View CA, US
Weiping Liao - Fremont CA, US
Benjamin Dodge - San Jose CA, US
Albert Meixner - Mountain View CA, US
Allan Douglas Knies - Burlingame CA, US
Manu Gulati - Saratoga CA, US
Rahul Jagdish Thakur - Santa Clara CA, US
Jason Rupert Redgrave - Mountain View CA, US
International Classification:
G06F 13/16
G06F 12/0815
G06F 12/0877
G06F 12/0811
Abstract:
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Apparatus And Method For Efficiently Implementing A Processor Pipeline

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US Patent:
20150378731, Dec 31, 2015
Filed:
Jun 30, 2014
Appl. No.:
14/319265
Inventors:
PATRICK P. LAI - Fremont CA, US
ETHAN SCHUCHMAN - Santa Clara CA, US
DAVID KEPPEL - Seattle WA, US
POLYCHRONIS XEKALAKIS - Santa Clara CA, US
JOSHUA B. FRYMAN - Corvallis OR, US
ALLAN D. KNIES - Burlingame CA, US
NAVEEN NEELAKANTAM - Mountain View CA, US
GREGOR STELLPFLUG - Braunschweig, DE
JOHN H. KELM - Sunnyvale CA, US
MIREM HYUSEINOVA - Barcelona, ES
DEMOS PAVLOU - Barcelona, ES
JAROSLAW TOPP - Schoeppenstedt, DE
International Classification:
G06F 9/30
G06F 15/76
Abstract:
Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.
Control profile
Allan D Knies from Burlingame, CA, age ~58 Get Report