US Patent:
20150378731, Dec 31, 2015
Inventors:
PATRICK P. LAI - Fremont CA, US
ETHAN SCHUCHMAN - Santa Clara CA, US
DAVID KEPPEL - Seattle WA, US
POLYCHRONIS XEKALAKIS - Santa Clara CA, US
JOSHUA B. FRYMAN - Corvallis OR, US
ALLAN D. KNIES - Burlingame CA, US
NAVEEN NEELAKANTAM - Mountain View CA, US
GREGOR STELLPFLUG - Braunschweig, DE
JOHN H. KELM - Sunnyvale CA, US
MIREM HYUSEINOVA - Barcelona, ES
DEMOS PAVLOU - Barcelona, ES
JAROSLAW TOPP - Schoeppenstedt, DE
International Classification:
G06F 9/30
G06F 15/76
Abstract:
Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.