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Ali Muhtaroglu

from Hillsboro, OR
Age ~51
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Also known as:
Habibe Muhtaroglu, Ali U
Phone and address:
6159 Copper Beech Dr, Beaverton, OR 97124
(503) 648-0105
Related to:
Habibe Muhtaroglu, 49
Connected to:
Marvin W Muhumuza, 45Frank G Muhvich, 81John Muhvich, 115Adrian Mui, 34Benjamin Mui, 35Bonnie L Mui, 70Bonny Mui, 36Chi Y Mui, 55Chris W Mui, 30

Ali Muhtaroglu Phones & Addresses

  • 6159 Copper Beech Dr, Hillsboro, OR 97124 (503) 648-0105
  • 6159 NE Copper Beech Dr APT H3, Hillsboro, OR 97124 (541) 556-3519
  • Beaverton, OR
  • 127 Dryden Rd, Ithaca, NY 14850
  • San Jose, CA

Publications

Us Patents

Structural Input Levels Testing Using On-Die Levels Generators

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US Patent:
7036061, Apr 25, 2006
Filed:
Aug 28, 2001
Appl. No.:
09/941484
Inventors:
Ali Muhtaroglu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/28
US Classification:
714727, 714734
Abstract:
A set of levels generating circuits, such as a set of digital-to-analog converters, is designed into an integrated circuit on-die. The levels generating circuits apply direct current (DC) voltage levels to on-die sense amplifiers to test sense amplifier trip points for “input low voltage” (VIL) and “input high voltage” (VIH). The levels generating circuits are controlled by a set of configuration bits, which may be accessible through the boundary-scan register or the input/output (I/O) loop back pattern generator. The levels generating circuitry allows testing of one number of integrated circuit input pins using a smaller number of input pins.

Method And Apparatus For On-Die Voltage Fluctuation Detection

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US Patent:
7157924, Jan 2, 2007
Filed:
Oct 10, 2003
Appl. No.:
10/683189
Inventors:
Ali Muhtaroglu - Hillsboro OR, US
Kent Callahan - Hillsboro OR, US
Tawfik Arabi - Tigard OR, US
Greg F. Taylor - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G01R 31/26
US Classification:
324765
Abstract:
An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.

Methods And Apparatuses For Validating Ac I/O Loopback Tests Using Delay Modeling In Rtl Simulation

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US Patent:
7228515, Jun 5, 2007
Filed:
May 13, 2004
Appl. No.:
10/846721
Inventors:
Bruce Querbach - Orangevale CA, US
Amjad Khan - Folsom CA, US
Mike Tripp - Forest Grove OR, US
Luis Briceno Guerrero - San Jose, CR
Marco A. Vindas Vargas - San Jose, CR
Ali Muhtaroglu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/45
G06F 17/50
US Classification:
716 6, 716 4, 716 5, 716 18
Abstract:
Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

Per Die Voltage Programming For Energy Efficient Integrated Circuit (Ic) Operation

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US Patent:
7685445, Mar 23, 2010
Filed:
Jun 29, 2006
Appl. No.:
11/478475
Inventors:
Tawfik Arabi - Tigard OR, US
Ali Muhtaroglu - Hillsboro OR, US
Michael Bitan - Misgav, IL
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/32
US Classification:
713320, 713300
Abstract:
Methods and apparatus to provide per die voltage programming for energy efficient integrated circuit (IC) operation are described. In some embodiments, the voltage potential supplied to an IC component is lowered below a peak performance voltage level, e. g. , to reduce power consumption by the component. Other embodiments are also described.

Per Die Temperature Programming For Thermally Efficient Integrated Circuit (Ic) Operation

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US Patent:
8461895, Jun 11, 2013
Filed:
Oct 25, 2011
Appl. No.:
13/281319
Inventors:
Tawfik Arabi - Tigard OR, US
Ali Muhtaroglu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1/04
H03K 3/00
US Classification:
327291, 327299, 713300, 713320
Abstract:
Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e. g. , to reduce power consumption and/or improve performance. Other embodiments are also described.

Per Die Temperature Programming For Thermally Efficient Integrated Circuit (Ic) Operation

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US Patent:
8044697, Oct 25, 2011
Filed:
Jun 29, 2006
Appl. No.:
11/478472
Inventors:
Tawfik Arabi - Tigard OR, US
Ali Muhtaroglu - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H03K 3/00
US Classification:
327299, 327291, 713320
Abstract:
Methods and apparatus to provide per die temperature programming for thermally efficient integrated circuit (IC) operation are described. In some embodiments, the junction temperature of an IC component is determined, e. g. , to reduce power consumption and/or improve performance. Other embodiments are also described.

Method And Apparatus For On-Die Voltage Fluctuation Detection

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US Patent:
20030112027, Jun 19, 2003
Filed:
Dec 19, 2001
Appl. No.:
10/021055
Inventors:
Ali Muhtaroglu - Hillsboro OR, US
Kent Callahan - Hillsboro OR, US
Tawfik Arabi - Tigard OR, US
Greg Taylor - Portland OR, US
International Classification:
G01R031/26
US Classification:
324/765000
Abstract:
An on-die device is provided to measure/detect voltage fluctuations. This may include a control unit to generate differential reference signals (such as differential current signals), a first detector unit and a second detector unit. The differential reference signals may be generated based on a Vcc reference signal and a Vss reference signal. The first detector unit may receive the differential reference signals from the control unit and may receive first voltage signals (also called monitored signals) from a first device under test (DUT) located on the die or from a first area on the die. The first detector unit may provide (or output) a first signal indicative of a voltage fluctuation (voltage droop or overshoot) of the first voltage signals. The second detector unit may receive the differential reference signals from the control unit and may receive second voltage signals (also called monitored signals) from a second device under test (DUT) located on the die. The second detector unit may provide (or output) a second signal indicative of a voltage fluctuation (or voltage droop) of the second voltage signals.
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Ali Muhtaroglu from Hillsboro, OR, age ~51 Get Report