Search

Ali Iranli

from Cupertino, CA
Age ~48
Get Report
Also known as:
Iranli Ali
Phone and address:
20488 Stevens Creek Blvd APT 2201, Cupertino, CA 95014
Related to:
Sepideh Iranli
Connected to:
Sima Iranmanesh, 69Tomik T Iranosian, 42Harmik Iranossian, 39Gul B Iranpur, 75Meital Irany, 49Enrique R Iranzo, 62Jose H Iranzo, 76Andrea D Irao, 58Jasmine Iraola, 33Joell Iraola, 33

Ali Iranli Phones & Addresses

  • 20488 Stevens Creek Blvd APT 2201, Cupertino, CA 95014
  • San Diego, CA
  • 477 S El Molino Ave APT 4, Pasadena, CA 91101
  • Los Angeles, CA
  • La Jolla, CA
  • 477 S El Molino Ave APT 4, Pasadena, CA 91101 (626) 584-6025

Work

Company: Qualcomm 2006 Address: Greater San Diego Area Position: System architect / staff engineer

Education

School / High School: University of Southern California 2000 to 2005

Skills

Computer Architecture • Mixed Signal • Semiconductors • Vlsi • Asic • Integrated Circuit Design • Verilog • Digital Signal Processors • Signal Processing • Serdes • Soc • System Architecture • Low Power Design • Ic • Processors • Software Development • Power Management • High Performance Computing • Cmos • Gpgpu • Simulations

Emails

a***[email protected]

Industries

Semiconductors

Resumes

Resumes

Ali Iranli Photo 1

Soc Architect And Performance Analysis Lead

View page
Location:
7715 Marker Rd, San Diego, CA 92130
Industry:
Semiconductors
Work:
Qualcomm - Greater San Diego Area since 2006
System Architect / Staff Engineer
Education:
University of Southern California 2000 - 2005
Sharif University of Technology
Skills:
Computer Architecture
Mixed Signal
Semiconductors
Vlsi
Asic
Integrated Circuit Design
Verilog
Digital Signal Processors
Signal Processing
Serdes
Soc
System Architecture
Low Power Design
Ic
Processors
Software Development
Power Management
High Performance Computing
Cmos
Gpgpu
Simulations

Publications

Us Patents

System And Method Of Monitoring A Central Processing Unit In Real Time

View page
US Patent:
8352759, Jan 8, 2013
Filed:
Aug 19, 2010
Appl. No.:
12/859424
Inventors:
Steven S. Thomson - San Diego CA, US
Ali Iranli - San Diego CA, US
Michael J. Drop - San Diego CA, US
Vinodh R. Cuppu - Oceanside CA, US
Christopher Kong Yee Chun - Austin TX, US
Tao Xue - San Diego CA, US
Moinul H. Kahn - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 1/00
US Classification:
713300, 713320
Abstract:
A method of monitoring one or more central processing units in real time is disclosed. The method may include monitoring state data associated with the one or more CPUs in real-time, filtering the state data, and at least partially based on filtered state data, selectively altering one or more system settings.

System And Method For Controlling Central Processing Unit Power In A Virtualized System

View page
US Patent:
8650426, Feb 11, 2014
Filed:
Nov 11, 2010
Appl. No.:
12/944202
Inventors:
Bohuslav Rychlik - San Diego CA, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Steven S. Thomson - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 1/00
US Classification:
713323
Abstract:
A method of dynamically controlling power within a multicore central processing unit is disclosed and includes executing a plurality of virtual cores, virtually executing one or more tasks, one or more threads, or a combination thereof at the virtual cores, and physically executing one or more tasks, one or more threads, or a combination thereof at a zeroth physical core. The method may further include receiving a degree of parallelism in a workload of a plurality of virtual cores and determining whether the degree of parallelism in the workload of the virtual cores is equal to a first wake condition.

Dynamic Backlight Scaling For Power Minimization In A Backlit Tft-Lcd

View page
US Patent:
20060209005, Sep 21, 2006
Filed:
Mar 2, 2006
Appl. No.:
11/367841
Inventors:
Massoud Pedram - Beverly Hills CA, US
Ali Iranli - Pasadena CA, US
International Classification:
G09G 3/36
US Classification:
345102000
Abstract:
An embodiment of the present invention is directed to a method for determining a pixel transformation function that maximizes backlight dimming while maintaining a pre-specified distortion level. The method includes determining a minimum dynamic range of pixel values in a transformed image based on an original image and the pre-specified distortion level and determining the pixel transformation function. The pixel transformation function takes a histogram of the original image to a uniform distribution histogram having the minimum dynamic range.

Systems And Methods For Reducing Power Consumption In A Device Through A Content Adaptive Display

View page
US Patent:
20080174607, Jul 24, 2008
Filed:
Jan 24, 2007
Appl. No.:
11/626580
Inventors:
Ali Iranli - San Diego CA, US
International Classification:
G09G 3/36
G02F 1/13357
US Classification:
345589, 345102
Abstract:
A method for reducing power consumption in a device through a content adaptive display is described. A frame of an image is received. A backlight value is calculated. A scaling factor is calculated. The backlight value is applied to a backlight. The scaling factor is applied to a matrix of pixels to obtain a scaled matrix of pixels. The scaled matrix of pixels is displayed.

System And Method For Controlling Central Processing Unit Power With Guaranteed Steady State Deadlines

View page
US Patent:
20110145559, Jun 16, 2011
Filed:
Nov 11, 2010
Appl. No.:
12/944516
Inventors:
Steven S. Thomson - San Diego CA, US
Bohuslav Rychlik - San Diego CA, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Norman S. Gargash - Boulder CO, US
International Classification:
G06F 9/00
US Classification:
713100
Abstract:
A method of dynamically controlling a central processing unit is disclosed. The method may include determining when a CPU enters a steady state, calculating an optimal frequency for the CPU when the CPU enters a steady state, guaranteeing a steady state CPU utilization, and guaranteeing a steady state CPU utilization deadline.

System And Method For Dynamically Controlling A Plurality Of Cores In A Multicore Central Processing Unit Based On Temperature

View page
US Patent:
20110145605, Jun 16, 2011
Filed:
Nov 11, 2010
Appl. No.:
12/944564
Inventors:
Sumit Sur - Boulder CO, US
Bohuslav Rychlik - San Diego CA, US
Steven S. Thomson - San Diego CA, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
International Classification:
G06F 1/26
US Classification:
713300
Abstract:
A method of controlling power within a multicore central processing unit (CPU) is disclosed. The method may include monitoring a die temperature, determining a degree of parallelism within a workload of the CPU, and powering one or more cores of the CPU up or down based on the degree of parallelism, the die temperature, or a combination thereof.

System And Method For Controlling Central Processing Unit Power Based On Inferred Workload Parallelism

View page
US Patent:
20110145615, Jun 16, 2011
Filed:
Nov 11, 2010
Appl. No.:
12/944140
Inventors:
Bohuslav Rychlik - San Diego CA, US
Robert A. Glenn - Boulder CO, US
Ali Iranli - San Diego CA, US
Brian J. Salsbery - Boulder CO, US
Sumit Sur - Boulder CO, US
Steven S. Thomson - San Diego CA, US
International Classification:
G06F 1/32
US Classification:
713323
Abstract:
A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.

System And Method For Controlling Central Processing Unit Power With Guaranteed Transient Deadlines

View page
US Patent:
20110145617, Jun 16, 2011
Filed:
Nov 11, 2010
Appl. No.:
12/944467
Inventors:
Steven S. Thomson - San Diego CA, US
Bohuslav Rychlik - San Diego CA, US
Ali Iranli - San Diego CA, US
Sumit Sur - Boulder CO, US
Norman S. Gargash - Boulder CO, US
International Classification:
G06F 1/32
US Classification:
713323
Abstract:
A method of controlling power at a central processing unit is disclosed. The method may include moving to a higher CPU frequency after a transient performance deadline has expired, entering an idle state, and resetting the transient performance deadline based on an effective transient budget.
Control profile
Ali Iranli from Cupertino, CA, age ~48 Get Report