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Alexander Bernhard Hoefler

from Austin, TX
Age ~56
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Also known as:
Alexander B Hoefler, Alexander B Hoelfer, Alexander B Hoefle
Phone and address:
6708 Lexington Rd, Austin, TX 78757
(512) 707-0315
Related to:
Darla DupreWilliam Thomas, 56Malynda M Dupre, 58Mary K
Connected to:
Dan L Hoefler, 62Floyd D Hoefler, 37Ray M Hoefler, 90Albert S Hoeflich, 60Tanner R Hoeflicker, 36Amanda R Hoeflinger, 41Brent A Hoefling, 57Chelsea M Hoeflinger, 35Jeremy A Hoefling, 41Joey J Hoefling, 47

Alexander Hoefler Phones & Addresses

  • 6708 Lexington Rd, Austin, TX 78757 (512) 707-0315
  • 2000 Point Bluff Dr, Austin, TX 78746
  • 12100 Metric Blvd, Austin, TX 78758 (512) 491-8673
  • 2503 Bridle Path, Austin, TX 78703
  • 2603 Rae Dell Ave, Austin, TX 78704 (512) 707-0315
  • 2602 Rae Dell Ave, Austin, TX 78704
  • 801 28Th St, Austin, TX 78705
  • 2504 12Th St, Austin, TX 78703
  • Round Rock, TX

Resumes

Resumes

Alexander Hoefler Photo 1

Staff Engineer

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Freescale Semiconductor Jul 2004 - Dec 2015
Staff Engineer
Nxp Semiconductors Jul 2004 - Dec 2015
Staff Engineer
Motorola 2001 - 2003
Simulation and Modeling Section Manager
Motorola 1997 - 2001
Tcad Simulation and Modeling Engineer
Abb 1991 - 1991
Summer Intern
Education:
Eth Zürich 1993 - 1997
University of Erlangen - Nuremberg 1987 - 1993
Skills:
Semiconductors
Alexander Hoefler Photo 2

Commission Analyst At Insight

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Alexander Hoefler Photo 3

Accounting Professional

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Publications

Us Patents

Write Operation For Capacitorless Ram

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US Patent:
6714436, Mar 30, 2004
Filed:
Mar 20, 2003
Appl. No.:
10/393053
Inventors:
James D. Burnett - Austin TX
Alexander Hoefler - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G11C 1124
US Classification:
365149, 365181, 365182
Abstract:
A method for writing data to single-transistor capacitorless (1T/0C) RAM cell, wherein the cell structure is predicated on an SOI MOS transistor that has a floating body region ( ). Data is written to the cell by the instigation of band-to-band tunneling (BTBT) and the resulting generation of hole/electron pairs. Electrons are drawn from the body region through forward-biased drain ( ) and source ( ) regions so that holes accumulate in the body region. The increase in threshold voltage, caused by the accumulation of holes, may be defined and detected as a logic level (ONE, for example). In one embodiment, a split biasing scheme applies substantially identical voltages to the drain and to the source and a negative bias to the gate. In alternative embodiments, a negative gate bias is not required and the drain and source bias voltages may be offset so as to mitigate source damage.

Multi-Bit Non-Volatile Memory Cell And Method Therefor

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US Patent:
6724032, Apr 20, 2004
Filed:
Jul 25, 2002
Appl. No.:
10/202697
Inventors:
Gowrishankar L. Chindalore - Austin TX
James D. Burnett - Austin TX
Alexander B. Hoefler - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 27108
US Classification:
257304, 257315, 257316, 257321, 257345
Abstract:
A non-volatile multiple bit memory ( ) has electrically isolated storage elements ( ) that overlie a channel region having a central area ( ) with high impurity concentration. A planar gate ( ) overlies the storage elements. The high impurity concentration may be formed by a centrally located region ( ) or by two peripheral regions ( ) having lower impurity concentration than the central portion of the channel. During a read or program operation, the channel area of high impurity concentration effectively controls a channel depletion region to enhance reading or programming of stored data bits. During a hot carrier program operation, the channel area of high impurity concentration enhances the programming efficiency by decreasing leakage currents in a memory array.

Program And Erase In A Thin Film Storage Non-Volatile Memory

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US Patent:
6791883, Sep 14, 2004
Filed:
Jun 24, 2002
Appl. No.:
10/178658
Inventors:
Craig T. Swift - Austin TX
Jane A. Yater - Austin TX
Alexander B. Hoefler - Austin TX
Ko-Min Chang - Austin TX
Erwin J. Prinz - Austin TX
Bruce L. Morton - Austin TX
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 1600
US Classification:
36518529, 36518518, 36518528
Abstract:
A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.

Split-Gate Thin-Film Storage Nvm Cell

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US Patent:
6828618, Dec 7, 2004
Filed:
Oct 30, 2002
Appl. No.:
10/283748
Inventors:
Alexander Hoefler - Austin TX
Erwin J. Prinz - Austin TX
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 2976
US Classification:
257311, 257314, 257315, 257316
Abstract:
A semiconductor nonvolatile memory cell ( ) comprising a split-gate FET device having a charge-storage transistor ( ) in series with a select transistor ( ). A multilayered charge-storage gate dielectric ( ) extends over at least a portion of the source ( ) and a first portion ( ) of the channel of the FET. A select gate dielectric ( ), contiguous to the charge-storage gate dielectric, extends over at least a portion of the drain ( ) and a second portion ( ) of the channel. A monolithic gate conductor ( ) overlies both the charge-storage gate dielectric and the select gate dielectric. In an embodiment, the charge-storage gate dielectric is an ONO stack that incorporates a thin-film nitride charge-storage layer ( ). The select transistor operates to inhibit over-erasure of the NVM cell. The thin-film nitride charge-storage layer extends laterally over a substantial portion of the channel so as to enhance data retention by the cell.

Non-Volatile Memory Device And Method For Forming

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US Patent:
6887758, May 3, 2005
Filed:
Oct 9, 2002
Appl. No.:
10/267153
Inventors:
Gowrishankar L. Chindalore - Austin TX, US
Paul A. Ingersoll - Austin TX, US
Craig T. Swift - Austin TX, US
Alexander B. Hoefler - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/336
H01L029/788
US Classification:
438257, 257315
Abstract:
A semiconductor device () has a highly doped layer () having a first conductivity type uniformly implanted into the semiconductor substrate (). An oxide-nitride-oxide structure () is formed over the semiconductor substrate (). A halo region () having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source () and drain () having a second conductivity type are implanted into the substrate (). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region () on the drain side allows a higher programming speed, and the highly doped layer () allows the use of a short channel device.

Fuse And Method For Forming

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US Patent:
6911360, Jun 28, 2005
Filed:
Apr 29, 2003
Appl. No.:
10/425275
Inventors:
Chi Nan Brian Li - Austin TX, US
Alexander B. Hoefler - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/479
US Classification:
438238, 438281, 438467, 257379, 257529
Abstract:
An active fuse includes an active fuse geometry () that is used to form both a variable resistor () and a select transistor (). In one embodiment, the active fuse geometry is formed in a portion of an active region () of a semiconductor substrate (), and a select gate () is disposed over an end portion () of the active fuse geometry to form an integral select transistor () for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.

Multi-Bit Non-Volatile Integrated Circuit Memory And Method Therefor

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US Patent:
6939767, Sep 6, 2005
Filed:
Nov 19, 2003
Appl. No.:
10/716956
Inventors:
Alexander B. Hoefler - Austin TX, US
Ko-Min Chang - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/336
US Classification:
438267, 257315, 257316, 438257
Abstract:
A non-volatile memory () includes at least two buried bit lines () formed within a semiconductor substrate (), a charge storage layer () overlying the semiconductor substrate (); a control gate () overlying the charge storage layer (); an insulating liner () overlying the control gate; and first and second conductive sidewall spacer control gates (). Multiple programmable charge storage regions () and () are created within the charge storage layer () beneath respective ones of the control gate () and the first and second sidewall spacer control gates (). Also, the non-volatile memory () is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.

Device For Reducing Sub-Threshold Leakage Current Within A High Voltage Driver

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US Patent:
7113430, Sep 26, 2006
Filed:
May 31, 2002
Appl. No.:
10/158991
Inventors:
Alexander Hoefler - Round Rock TX, US
Khoi V. Dinh - Austin TX, US
Robert A. Jensen - Austin TX, US
Matthew B. Rutledge - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 16/08
US Classification:
36518523, 36518529, 36518518
Abstract:
A device for reducing the effects of leakage current within electronic devices is disclosed. In one form, a high voltage driver includes a high voltage source coupled to at least one high voltage transistor and a leakage offset module coupled to at least a portion of one of the high voltage transistors. The leakage offset module includes a diode connected MOS device operable to generate an offset voltage and an MOS shunting device coupled in a parallel with the diode connected MOS device. During operation, the diode connected MOS device generates an offset voltage based on a sub-threshold leakage associated with using the high voltage source and the MOS shorting device is operable to short the diode connected MOS device when sub-threshold leakage current is relatively low.
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Alexander Bernhard Hoefler from Austin, TX, age ~56 Get Report