Alexander J Branover

7856562, Dec 21, 2010

May 2, 2007

11/743341

Alexander Branover - Brookline MA, US
Maurice Steinman - Marlborough MA, US
Frank Helms - Austin TX, US
Bill K. C. Kwan - Austin TX, US
W. Kurt Lewchuk - Austin TX, US
Paul Mackey - Austin TX, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1/26

713300, 713320

A method includes applying a voltage to a first processor core of a plurality of processor cores to deactivate the first processor core, the voltage less than a retention voltage of the first processor core. The application of the voltage can be in response to a software setting. The software setting can be configured via a user input, a software application, an operating system, or a BIOS setting. Alternately, the application of the voltage can be in response to a permanent hardware setting, such as the state of a fuse associated with the first processor core.

8028185, Sep 27, 2011

Mar 11, 2008

12/045764

Alexander Branover - Brookline MA, US
Rajen S. Ramchandani - Arlington MA, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G06F 1/00

713330, 710262

A processor may comprise one or more cores, where each respective core may comprise one or more state registers, and non-volatile memory configured to store microcode instructions executed by the respective processor core. The processor may further comprise a power management controller (PMC) interfacing with each respective core, and a state monitor (SM) interfacing with the PMC. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a low-power state. The microcode may communicate the request to the PMC, which may in turn determine if the request is for the respective core to transition to a zero-power state. If it is, the PMC may communicate with the SM to determine whether to transition the respective processor core to the zero-power state, and initiate transition to the zero-power state if a determination to transition to the zero-power state is made.

8112647, Feb 7, 2012

Oct 20, 2008

12/254650

Alexander Branover - Chestnut Hill MA, US
Frank P. Helms - Austin TX, US
John P. Petry - San Diego CA, US
Maurice B. Steinman - Marlborough MA, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G06F 1/26

713320, 710260

A system may comprise a plurality of processing units, and a control unit and monitoring unit interfacing with the processing units. The control unit may receive requests for transitioning the processing units to respective target power-states, and specify respective target HW power-states corresponding to the respective target power-states. The monitoring unit may monitor operating characteristics of the system, and determine based on operating characteristics whether to allow the processing units to transition to the respective target hardware (HW) power-states. The control unit may be configured to change the respective target HW power-state to a respective updated HW power-state for each processing units for which it is determined that transition to its respective target HW power-state should not be allowed. The control unit may also be configured to infer a common target HW power-state based on the respective target HW power-states of processing units of a subset of the plurality of processing units, when the processing units of the subset of the plurality of processing units share at least one resource domain.

8112648, Feb 7, 2012

Dec 12, 2008

12/333744

Alexander Branover - Chestnut Hill MA, US
Maurice B. Steinman - Marlborough MA, US
Denis Rystsov - Arlington MA, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G06F 1/26

713320, 718100

A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.

8156362, Apr 10, 2012

Aug 27, 2008

12/198974

Alexander Branover - Chestnut Hill MA, US
Frank Helms - Austin TX, US
Maurice Steinman - Marlborough MA, US

GLOBALFOUNDRIES Inc. - Grand Cayman

G06F 1/00

713330, 710262

A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

8291249, Oct 16, 2012

Sep 25, 2009

12/566930

Alexander Branover - Chestnut Hill MA, US
Denis Rystsov - Arlington MA, US
Maurice B. Steinman - Marlborough MA, US
Jonathan M. Owen - Northborough MA, US
Denis J. Foley - Shrewsbury MA, US

Advanced Micro Devices, Inc. - Austin TX

G06F 1/32

713323, 713320

A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

8412971, Apr 2, 2013

May 11, 2010

12/777657

Alexander Branover - Chestnut Hill MA, US
Norman M. Hack - Pflugerville TX, US
Maurice B. Steinman - Marlborough MA, US
John Kalamatianos - Arlington MA, US
Jonathan M. Owen - Northborough MA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1/26

713324, 713323, 713330, 711118

A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

8438416, May 7, 2013

Oct 21, 2010

12/909006

Andrej Kocev - York ME, US
Alexander Branover - Chestnut Hill MA, US

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 1/32
G06F 1/10

713601, 713322, 713323, 713324

A system and method for dynamic function based power control is disclosed. In one embodiment, a system includes a bridge unit having a memory controller and a communication hub coupled to the memory controller. The system further includes a power management unit, wherein the power management unit is configured to clock-gate the communication hub responsive to determining that each of a plurality of processor cores are in an idle state and that an I/O interface unit has been idle for an amount of time exceeding a first threshold. The power management unit is further configured to clock-gate the memory controller responsive to clock-gating the communication hub and determining that a memory coupled to the memory controller is in a first low power state. The power management unit may also perform power-gating of functional units subsequent to clock-gating the same.